Method for booting a heterogeneous system and presenting a symmetric core view

Patent metadata

Field	Value
Publication number	US-10503517-B2
Application number	US-201715672254-A
Country	US
Kind code	B2
Filing date	Aug 8, 2017
Priority date	Mar 15, 2013
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

First claim

What is claimed is:

1. A processor comprising:
a first physical core having a first instruction set and a first power consumption level, to execute a thread at a first performance level;
a second physical core having a second instruction set and a second power consumption level, to execute a thread at a second performance level, the first and second cores being in a dynamic multi-core unit; and
a virtual-to-physical (V-P) mapping circuit coupled to the first and second physical cores, to map the first physical core to a system firmware interface via a virtual core and to hide the second processor core from the system firmware interface.

2. The processor as in claim 1 further comprising a third physical core having the first instruction set and the first power consumption level, wherein the V-P mapping circuit is to map a first virtual core to the first physical core and to map a second virtual core to the third physical core, to allow a set of threads to be executed in parallel across the first and third physical processor cores.

3. The processor as in claim 2 wherein the V-P mapping logic is to map the second virtual core to the second physical core transparently to the firmware interface in response to detected characteristics associated with the set of threads being executed.

4. The processor as in claim 3 wherein the first power consumption level is lower than the second power consumption level.

5. The processor as in claim 4 wherein the second performance level is higher than the first performance level.

6. The processor as in claim 5 wherein the second physical core is made accessible to software by the V-P mapping circuit by mapping one or more of the virtual cores to the second physical core.

7. The processor as in claim 1 wherein a single physical core of the processor acts as a bootstrap processor.

8. The processor as in claim 7 wherein the first physical core acts as the bootstrap processor.

9. The processor as in claim 8 wherein the bootstrap processor initializes the second physical core.

10. A method comprising:
providing a set of one or more small physical processor cores;
providing at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores;
exposing a set of two or more small physical processor cores to a system firmware interface; and
hiding the at least one large physical processor core from the system firmware interface.

11. The method as in claim 10 further comprising:
dynamically swapping a thread from a first small physical processor core to a large physical processor core, to allow the threads to be executed in on the large physical processor core, wherein the swapping is transparent to the thread.

12. The method as in claim 10 further comprising:
nominating a small physical processor core from the set of small physical processor cores as a bootstrap processor;
initializing, by the bootstrap processor, each processor in the set of small physical cores; and
initializing, by the bootstrap processor the at least one large physical core.

13. The method as in claim 12 wherein the small physical processor cores are exposed to the software through a default mapping between virtual processors and small physical processor cores.

14. The method as in claim 13 wherein the at least one large physical processor core is hidden from the system firmware interface and made accessible to an operating system by transparently mapping one or more of the virtual cores to the large physical processor cores.

15. The method as in claim 14 wherein the large physical processor is visible to an operating system having support for processor cores having multiple instruction sets.

Assignees

• Intel Corp

Inventors

• Weissmann Eliezer
• Rappoport Rinat
• Mishaeli Michael
• Shafi Hisham
• Lenz Oron
• Brandt Jason W
• Fischer Stephen A
• Toll Bret L
• Sodhi Inder M
• Naveh Alon
• Srinivasa Ganapati N
• Choubal Ashish V
• Hahn Scott D
• Koufaty David A
• Fenger Russel J
• Khanna Gaurav
• Gorbatov Eugene
• Naik Mishali
• Herdrich Andrew J
• Prabhakaran Abirami
• Sahagirdar Sanjeev S
• Brett Paul
• Narvaez Paolo
• Henroid Andrew D
• Subbareddy Dheeraj R

Classifications

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/5044

  considering hardware capabilities · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title