Method and apparatus for a zero voltage processor sleep state

Patent metadata

Field	Value
Publication number	US-9870044-B2
Application number	US-201615280057-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Jul 27, 2004
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

First claim

What is claimed is:

1. A system comprising:
at least one processor comprising a first core and a second core;
voltage regulation circuitry to regulate an operational voltage of the first core and the second core;
an interconnect to couple one of the at least one processor to one or more system components; and
a system memory coupled to one of the at least one processor,
one of the at least one processor comprising:
the first core to execute sequences of instructions;
the second core to execute sequences of instructions;
a shared cache accessible by both the first core and the second core;
power management logic to cause the first core to be powered down in a first mode while the second core remains in an active state;
wherein power to the shared cache is to be maintained to enable access by the second core; and
wherein data associated with the first core is to be preserved when the first core is powered down in the first mode, and in a second mode the first core and the second core are to be powered down and the at least one processor is to enter a package sleep state.

2. The system of claim 1 , wherein at least one instruction of the sequences of instructions is a sleep instruction.

3. The system of claim 2 , wherein the sleep instruction is to cause certain portions of the at least one processor to be powered down.

4. The system of claim 2 , wherein the sleep instruction is to cause certain clocks to be gated.

5. The system of claim 1 , wherein the system memory comprises a random access memory.

6. The system of claim 1 , further comprising:
at least one communication device coupled to the at least one processor.

7. The system of claim 1 , wherein the voltage regulation circuitry is integrated in the at least one processor.

8. The system of claim 1 , wherein the at least one processor further comprises a vector to store an identification of one or more registers to be saved before the first core is to be powered down.

9. The system of claim 8 , wherein the at least one processor further comprises microcode to access the vector and to store a state of one or more registers to the shared cache.

10. The system of claim 1 , wherein in the at least one processor further comprises a memory to store a voltage identification value.

11. The system of claim 1 , wherein the first mode comprises a core C6 state and the second mode comprises a C6 state.

12. A system comprising:
at least one processor means comprising a first core and a second core;
voltage regulation means to regulate an operational voltage of the first core and the second core;
interconnect means to couple one of the at least one processor means to one or more system components; and
system memory means coupled to the at least one processor means,
one of the at least one processor means comprising:
the first core to execute sequences of instructions;
the second core to execute sequences of instructions;
shared cache means accessible by both the first core and the second core;
power management means to cause the first core to be powered down in a first mode while the second core remains in an active state;
wherein power to the shared cache means is to be maintained to enable access by the second core; and
wherein data associated with the first core is to be preserved when the first core is powered down in the first mode, and in a second mode the first core and the second core are to be powered down and the at least one processor means is to enter a package sleep state.

13. The system of claim 12 , wherein at least one instruction of the sequences of instructions is a sleep instruction.

14. The system of claim 13 , wherein the sleep instruction is to cause certain portions of the at least one processor means to be powered down.

15. The system of claim 13 , wherein the sleep instruction is to cause certain clocks to be gated.

16. The system of claim 12 , further comprising:
at least one communication device means coupled to the at least one processor means.

17. The system of claim 12 , further comprising:
at least one storage device means coupled to the at least one processor means.

18. A method comprising:
regulating a voltage of first and second cores of a processor with a voltage regulation circuit;
interconnecting the processor to one or more system components; and
coupling a system memory to the processor,
the processor comprising:
the first core to execute sequences of instructions;
the second core to execute sequences of instructions;
shared cache circuitry accessible by both the first core and the second core;
power management circuitry to cause the first core to be powered down while the second core remains in an active state;
wherein power to the shared cache circuitry is to be maintained to enable access by the second core, and when the second core is to be powered down, a size of the shared cache circuitry is reduced; and
wherein data associated with the first core is to be preserved when the first core is powered down.

19. The method of claim 18 , wherein at least one instruction of the sequences of instructions is a sleep instruction.

20. The method of claim 19 , wherein the sleep instruction is to cause certain portions of the processor to be powered down.

21. The method of claim 19 , wherein the sleep instruction is to cause certain clocks to be gated.

Assignees

• Intel Corp

Inventors

• Jahagirdar Sanjeev
• George Varghese
• Conrad John B
• Milstrey Robert
• Fischer Stephen A
• Naveh Alon
• Rotem Shai

Classifications

• Y02B60/1239

  Cross-Sectional Technologies · mapped topic

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• Y10T307/406

  Cross-Sectional Technologies · mapped topic

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title