Method for booting a heterogeneous system and presenting a symmetric core view

Patent metadata

Field	Value
Publication number	US-9727345-B2
Application number	US-201313854001-A
Country	US
Kind code	B2
Filing date	Mar 29, 2013
Priority date	Mar 15, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

First claim

What is claimed is:

1. A processor comprising:
a first physical core, having a first instruction set and a first power consumption level, to execute a thread at a first performance level, wherein the first physical core is to act as a bootstrap processor;
a second physical core, having a second instruction set and a second power consumption level, to execute a thread at a second performance level, the first and second cores being in a dynamic multi-core unit;
a third physical core having the first instruction set and the first power consumption level; and
a virtual-to-physical (V-P) mapping circuit, coupled to the first, second, and third physical cores, to map the first and third physical cores to a system firmware interface via a first and second virtual core respectively and to hide the second processor core from the system firmware interface and an operating system, wherein after the second physical core has performed an initialization sequence it enters a masked power state in which the second processor core is placed into a low power state and it not accessible by system triggers, and wherein the first and third physical cores are accessible by system triggers.

2. The processor as in claim 1 wherein the V-P mapping logic is to map the second virtual core to the second physical core transparently to the firmware interface in response to detected characteristics associated with the set of threads being executed.

3. The processor as in claim 2 wherein the first power consumption level is lower than the second power consumption level.

4. The processor as in claim 3 wherein the second performance level is higher than the first performance level.

5. The processor as in claim 4 wherein the second physical core is made accessible to software by the V-P mapping circuit by mapping one or more of the virtual cores to the second physical core.

6. The processor as in claim 1 wherein the bootstrap processor initializes the second physical core.

7. A method comprising:
exposing a set of two or more small physical processor cores to a system firmware interface; and
hiding at least one large physical processor core from the system firmware interface and an operating system, wherein the at least one large physical processor core has relatively higher performance processing capabilities and relatively higher power usage relative to the set of two or more small physical processor cores, wherein after the large physical core has performed an initialization sequence it enters a masked power state in which the large processor core is placed into a low power state and it not accessible by system triggers, and wherein the set of small physical cores is accessible by system triggers.

8. The method as in claim 7 further comprising:
dynamically swapping a thread from a first small physical processor core to a large physical processor core, to allow the threads to be executed in on the large physical processor core, wherein the swapping is transparent to the thread.

9. The method as in claim 7 further comprising:
nominating a small physical processor core from the set of small physical processor cores as a bootstrap processor;
initializing, by the bootstrap processor, each processor in the set of small physical cores; and
initializing, by the bootstrap processor the at least one large physical core.

10. The method as in claim 9 wherein the small physical processor cores are exposed to the software through a default mapping between virtual processors and small physical processor cores.

11. The method as in claim 10 wherein the at least one large physical processor core is hidden from the system firmware interface and made accessible to an operating system by transparently mapping one or more of the virtual cores to the large physical processor cores.

12. The method as in claim 11 wherein the large physical processor is visible to an operating system having support for processor cores having multiple instruction sets.

13. A system comprising:
a set of at least two small physical processor cores;
one or more large physical processor cores having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores;
virtual-to-physical (V-P) mapping logic to expose the set of at least two small physical processor cores to a system firmware interface through a corresponding set of virtual cores and to hide the at least one large physical processor core from the system firmware and an operating system, wherein after the large physical core has performed an initialization sequence it enters a masked power state in which the large processor core is placed into a low power state and it not accessible by system triggers, and wherein the set of small physical cores is accessible by system triggers; and
a package unit, to nominate and initialize a bootstrap processor selected from the set of multiple small physical processor cores.

14. The system as in claim 13 , wherein the V-P mapping logic is to map each virtual core to a physical core within the set of two or more small physical processor cores to allow a first set of threads to be executed in parallel across the small physical processor cores.

15. The system as in claim 14 , further including a bootstrap processor selected from one of the physical processor cores, wherein the bootstrap processor:
initializes each processor in the set of small physical cores; and
initializes the at least one large physical core.

16. The system as in claim 15 , wherein the at least one large physical core includes a masked idle state, in which the at least one large physical core is not mapped to a virtual core when the at least one large physical core is in the masked idle state.

17. The system as in claim 16 , wherein the bootstrap processor is a small physical core.

Assignees

• Intel Corp

Inventors

• Weissmann Eliezer
• Rappoport Rinat
• Mishaeli Michael
• Shafi Hisham
• Lenz Oron
• Brandt Jason W
• Fischer Stephen A
• Toll Bret L
• Sodhi Inder M
• Naveh Alon
• Srinivasa Ganapati N
• Choubal Ashish V
• Hahn Scott D
• Koufaty David A
• Fenger Russell J
• Khanna Gaurav
• Gorbatov Eugene
• Naik Mishali
• Herdrich Andrew J
• Prabhakaran Abirami
• Sahagirdar Sanjeev S
• Brett Paul
• Narvaez Paolo
• Henroid Andrew D
• Subbareddy Dheeraj R

Classifications

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F9/50 Primary

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/5044

  considering hardware capabilities · CPC title