Protection against return oriented programming attacks

Patent metadata

Field	Value
Publication number	US-10049212-B2
Application number	US-201514861210-A
Country	US
Kind code	B2
Filing date	Sep 22, 2015
Priority date	Sep 28, 2012
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.

First claim

What is claimed is:

1. A processor comprising:
a core including a fetch unit to fetch instructions, a decode unit to decode the fetched instructions, at least one execution unit to execute one or more of the decoded instructions and a first logic comprising at least one hardware circuit coupled to the at least one execution unit, the first logic to:
in response to a first instruction of an instruction set architecture (ISA):
generate a check value using a secret value stored in a secure storage, wherein the secret value corresponds to a salt value based on a ROP security level;
push the check value and a return pointer onto a call stack, wherein the secret value is not pushed onto the call stack;

in response to a second instruction of the ISA:
pop the return pointer and the check value off the call stack;
retrieve the secret value from the secure storage;
generate a validation check value using the secret value retrieved from the secure storage;
compare the check value to the validation check value generated using the secret value retrieved from the secure storage; and
determine that the check value is valid responsive to a match between the check value and the validation check value generated using the secret value retrieved from the secure storage.

2. The processor of claim 1 , wherein the secret value is only accessible to an operating system, the secret value to be generated at a beginning of a session, wherein the secure storage is a protected register.

3. The processor of claim 1 , wherein, in response to determination that the check value is valid, the processor is to resume execution at a location specified by the return pointer, and otherwise indicate a possible Return Oriented Programming (ROP) attack.

4. The processor of claim 1 , wherein the first instruction is a checked call instruction of the ISA, and the second instruction of the ISA is a checked return instruction of the ISA.

5. The processor of claim 1 , wherein the first logic is to generate the secret value under control of an operating system, responsive to a third instruction of the ISA, wherein the third instruction is reserved for use by the operating system.

6. The processor of claim 5 , wherein the first logic is to, responsive to the third instruction of the ISA, generate the secret value based on a random number function and store the secret value in the secure storage.

7. The processor of claim 1 , wherein the first logic is to:
combine the secret value with a first operand including the return pointer to obtain a first combined value;
obtain a first hash sum of the first combined value;
combine the secret value with a second value to obtain a second combined value;
obtain a second hash sum of the second combined value and the first hash sum; and
obtain the check value from the second hash sum.

8. The processor of claim 1 , wherein the first logic is to generate the check value by at least one of encryption of the secret value with the return pointer, and encryption of the secret value with a stack pointer.

9. The processor of claim 1 , wherein the return pointer and the check value generated using the secret value are pushed onto different levels of the call stack.

10. The processor of claim 1 , wherein, in response to determination that the check value is valid, the processor is to validate that the return pointer is not part of a Return Oriented Programming (ROP) attack.

11. At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:
obtain, via a first logic of a processor, a check value and a return pointer from a call stack stored in a memory, wherein the processor comprises a control register including at least one bit to indicate whether the first logic is enabled;
retrieve a secret value from a secure location, wherein the secret value is not stored in the call stack, wherein the secret value corresponds to a salt value based on a return oriented programming (ROP) security level;
generate a validation check value using the secret value retrieved from the secure storage;
determine whether the check value obtained from the call stack matches the validation check value generated from the secret value retrieved from the secure location; and
in response to a determination that the check value matches the validation check value generated from the secret value, execute the return pointer, wherein the check value is associated with the return pointer.

12. The at least one non-transitory computer readable medium of claim 11 , further comprising a first instruction that when executed causes the processor to:
generate the check value using the secret value in response to a call for a subroutine; and
store the return pointer and the check value on the call stack.

13. The at least one non-transitory computer readable medium of claim 11 , further comprising a second instruction that when executed causes the processor to:
obtain the return pointer and the check value from the call stack;
retrieve the secret value from the secure location;
generate the validation check value using the secret value retrieved from the secure location;
determine whether the check value obtained from the call stack matches the validation check value; and
in response to the determination that the check value obtained from the call stack matches the validation check value, execute the return pointer.

14. The at least one non-transitory computer readable medium of claim 11 , further comprising instructions that when executed enable the system to determine the ROP security level based on a level of ROP functionality of the processor.

15. The at least one non-transitory computer readable medium of claim 11 , further comprising instructions that when executed enable the system to, upon a determination that the check value does not match the validation check value, raise an exception without execution of the return pointer.

16. A processor comprising:
a plurality of cores;
at least one graphics engine;
a shared cache memory coupled to the plurality of cores and the at least one graphics engine;
a memory controller; and
wherein a first core of the plurality of cores comprises a first logic to:
in response to a first instruction of an instruction set architecture (ISA):
generate a check value using a secret value stored in a secure storage, wherein the secret value corresponds to a salt value based on a Return Oriented Programming (ROP) security level;
push the check value and a return pointer onto a call stack;

in response to a second instruction of the ISA:
pop the return pointer and the check value off the call stack;
retrieve the secret value from the secure storage;
generate a validation check value using the secret value retrieved from the secure storage;
compare the check value to the validation check value generated using the secret value retrieved from the secure storage; and
determine that the check value is valid responsive to a match between the check value and the validation check value generated from the secret value retrieved from the secure storage.

17. The processor of claim 16 , wherein, in response to determination that the check value is valid, the processor is to resume execution at a location specified by the return pointer, and otherwise indicate a possible ROP attack.

18. The processor of claim 16 , wherein, in response to determination that the check value is valid, the processor is to validate that the return pointer is not part of a ROP attack.

Assignees

• Intel Corp

Inventors

• Fischer Stephen A

Classifications

• G06F21/566 Primary

  Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities · CPC title

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• H04L63/14 Primary

  for detecting or protecting against malicious traffic · CPC title

• G06F2221/033

  Test or assess software · CPC title