Method and apparatus for a non-deterministic random bit generator (NRBG)

Patent metadata

Field	Value
Publication number	US-9544139-B2
Application number	US-201113976175-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.

First claim

What is claimed is:

1. An apparatus, comprising:
an interconnect;
a digital random number generator (DRNG) circuit to condition entropy data provided by an entropy source, to generate and output a plurality of deterministic random bit (DRB) strings, and to generate and output a plurality of nondeterministic random bit (NRB) strings, wherein the plurality of DRB and NRB strings are distinct strings;
an execution unit circuit coupled to the DRNG circuit, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction, and in response to a second instruction to read a random number, to retrieve one of the DRB strings from the DRNG circuit and to store the DRB in a destination register specified by the second instruction; and
a flag register to store a flag set by the execution unit to indicate whether the NRB string stored in the destination register is valid.

2. The apparatus of claim 1 , wherein the DRNG circuit comprises:
a conditioner to condition the entropy data provided by the entropy source to generate conditioned entropy (CE) data;
a DRB generator (DRBG) coupled to the conditioner to generate the DRB strings based on the CE data; and
an NRB generator (NRBG) coupled to the conditioner and the DRBG to generate the NRB strings based on the DRB strings and the CE data.

3. The apparatus of claim 2 , wherein the NRBG comprises an exclusive OR (XOR) logic to perform an XOR operation on the DRB strings and the CE data to generate the NRB strings.

4. The apparatus of claim 2 , further comprising:
a conditional entropy buffer to store the CE data;
a DRBG buffer to store the DRB strings; and
an NRBG buffer to store the NRB strings.

5. The apparatus of claim 4 , wherein the DRBG circuit is configured to automatically generate more DRB strings when a number of the DRB strings stored in the DRBG buffer drops below a first predetermined threshold.

6. The apparatus of claim 4 , wherein the NRBG is configured to automatically generate more NRB strings when a number of the NRB strings stored in the NRBG buffer drops below a second predetermined threshold.

7. A system, comprising:
an interconnect;
a processor coupled the interconnect, the processor including
a digital random number generator (DRNG) circuit to condition entropy data provided by an entropy source, to generate and output a plurality of deterministic random bit (DRB) strings, and to generate and output a plurality of nondeterministic random bit (NRB) strings, wherein the plurality of DRB and NRB strings are distinct strings,
an execution unit circuit coupled to the DRNG circuit, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG circuit and to store the NRB string in a destination register specified by the first instruction, and in response to a second instruction to read a random number, to retrieve one of the DRB strings from the DRNG circuit and to store the DRB in a destination register specified by the second instruction, and
a flag register to store a flag set by the execution unit to indicate whether the NRB string stored in the destination register is valid; and

a dynamic random access memory (DRAM) coupled to the interconnect.

8. The system of claim 7 , wherein the DRNG circuit comprises:
a conditioner to condition the entropy data provided by the entropy source to generate conditioned entropy (CE) data;
a DRB generator (DRBG) coupled to the conditioner to generate the DRB strings based on the CE data; and
an NRB generator (NRBG) coupled to the conditioner and the DRBG to generate the NRB strings based on the DRB strings and the CE data.

Assignees

• Cox George W
• Johnston David
• Dixon Martin G
• Fischer Stephen A
• Brandt Jason W
• Intel Corp

Inventors

• Cox George W
• Johnston David
• Dixon Martin G
• Fischer Stephen A
• Brandt Jason W

Classifications

• G06F7/588

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G06F2207/583

  Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• H04L9/0662 Primary

  with particular pseudorandom sequence generator · CPC title

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title