Resequencing data programmed to multiple level memory cells at a memory sub-system
US-12561080-B2 · Feb 24, 2026 · US
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Feeley Peter patents
Feeley Peter is listed as an inventor on 259 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Feeley Peter |
| Total patents | 259 |
| First publication | Mar 19, 2015 |
| Latest publication | Feb 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Selectable trim settings on a memory device
US-12542190-B2 · Feb 3, 2026 · US
Parity scheme for read distress protection in a memory system
US-2026031177-A1 · Jan 29, 2026 · US
Trim setting determination on a memory device
US-12511232-B2 · Dec 30, 2025 · US
Enhanced data protection schemes for memory systems
US-2025383964-A1 · Dec 18, 2025 · US
Buffer allocation for reducing block transit penalty
US-12498886-B2 · Dec 16, 2025 · US
Multiple-pass programming of memory cells using temporary parity generation
US-12481463-B2 · Nov 25, 2025 · US
Using a common pool of blocks for user data and a system data structure
US-12430243-B2 · Sep 30, 2025 · US
Logical to physical memory address mapping using bitmaps
US-2025291717-A1 · Sep 18, 2025 · US
Voltage bin calibration based on a voltage distribution reference voltage
US-12393363-B2 · Aug 19, 2025 · US
Recent patents
Latest publications not already listed above.
Trim setting determination for a memory device
US-12367942-B2 · Jul 22, 2025 · US
Block-efficient write policies for memory devices
US-2025181240-A1 · Jun 5, 2025 · US
Block family-based error avoidance for memory devices
US-2025181259-A1 · Jun 5, 2025 · US
Trim setting determination for a memory device
US-2025166719-A1 · May 22, 2025 · US
Block family-based error avoidance for memory devices
US-12307111-B2 · May 20, 2025 · US
Memory device with dynamic cache management
US-2025156319-A1 · May 15, 2025 · US
Data recovery in memory devices
US-2025147686-A1 · May 8, 2025 · US
Managing error-handling flows in memory devices
US-12229000-B2 · Feb 18, 2025 · US
Memory device with dynamic cache management
US-12216573-B2 · Feb 4, 2025 · US
Memory devices and systems including hybrid cache, and related methods
US-2025013364-A1 · Jan 9, 2025 · US
Buffer allocation for reducing block transit penalty
US-2024393980-A1 · Nov 28, 2024 · US
Memory devices and systems including static and dynamic caches, and related methods
US-12131020-B2 · Oct 29, 2024 · US
Memory block programming using defectivity information
US-2024347128-A1 · Oct 17, 2024 · US
Multiple-pass programming of memory cells using temporary parity generation
US-2024302999-A1 · Sep 12, 2024 · US
Buffer allocation for reducing block transit penalty
US-12079517-B2 · Sep 3, 2024 · US
Voltage calibration scans to reduce memory device overhead
US-12057185-B2 · Aug 6, 2024 · US
Memory block programming using defectivity information
US-12051479-B2 · Jul 30, 2024 · US
Voltage bin calibration based on a voltage distribution reference voltage
US-2024231676-A1 · Jul 11, 2024 · US
Trim setting determination on a memory device
US-2024211395-A1 · Jun 27, 2024 · US
Selectable trim settings on a memory device
US-2024203516-A1 · Jun 20, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 261 |
| Feeley Peter | 2 |
| Abraham Michael M | 1 |
| Dover Lance | 1 |
| Cooke Jim | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0246 | 118 |
| G11C16/10 | 102 |
| G06F3/064 | 90 |
| G06F3/0679 | 86 |
| G11C29/028 | 80 |