Voltage calibration scans to reduce memory device overhead

Patent metadata

Field	Value
Publication number	US-12057185-B2
Application number	US-202218083992-A
Country	US
Kind code	B2
Filing date	Dec 19, 2022
Priority date	Mar 11, 2021
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
initiating a voltage calibration scan with respect to a block of the memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin;
measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin;
determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets; and
in response to determining that the value is less than the current value, designating the second bin as the current bin.

2. The system of claim 1 , wherein the operations further comprise: in response to determining that the value is greater than or equal to the current value, maintaining the first bin as the current bin.

3. The system of claim 2 , wherein the operations further comprise:
initiating a second voltage calibration scan; and
measuring a second value of the data state metric for the block based on a third set of read voltage offsets associated with a third bin of blocks having an index value higher than the first bin.

4. The system of claim 3 , wherein the operations further comprise:
determining whether the second value does not exceed the first value; and
in response to determining that the third value does not exceed the first value, replacing the first bin with the third bin as the current bin.

5. The system of claim 1 , wherein the current bin has an index value higher than at least one other bin.

6. The system of claim 1 , wherein the data state metric is raw bit error rate.

7. The system of claim 1 , wherein the data state metric is a distance to an optimal valley associated with a shifted threshold voltage distribution.

8. A method comprising:
initiating, by a processing device, a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin;
measuring, by the processing device, a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin;
determining, by the processing device, whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets; and
in response to determining that the value is less than the current value, designating, by the processing device, the second bin as the current bin.

9. The method of claim 8 , further comprising: in response to determining that the value is greater than or equal to the current value, maintaining, by the processing device, the first bin as the current bin.

10. The method of claim 9 , further comprising:
initiating, by the processing device, a second voltage calibration scan; and
measuring, by the processing device, a second value of the data state metric for the block based on a third set of read voltage offsets associated with a third bin of blocks having an index value higher than the first bin.

11. The method of claim 10 , further comprising:
determining, by the processing device, whether the second value does not exceed the first value; and
in response to determining that the second value does not exceed the first value, replacing, by the processing device, the first bin with the third bin as the current bin.

12. The method of claim 8 , wherein the current bin has an index value higher than at least one other bin.

13. The method of claim 8 , wherein the data state metric is raw bit error rate.

14. The method of claim 8 , wherein the data state metric is a distance to an optimal valley associated with a shifted threshold voltage distribution.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin;
measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin;
determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets; and
in response to determining that the value is less than the current value, designating the second bin as the current bin.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise: in response to determining that the value is greater than or equal to the current value, maintaining the first bin as the current bin.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the operations further comprise:
initiating a second voltage calibration scan; and
measuring a second value of the data state metric for the block based on a third set of read voltage offsets associated with a third bin of blocks having an index value higher than the first bin.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the operations further comprise:
determining whether the second value does not exceed the first value; and
in response to determining that the third value does not exceed the first value, replacing the first bin with the third bin as the current bin.

19. The non-transitory computer-readable storage medium of claim 15 , wherein the current bin has an index value higher than at least one other bin.

20. The non-transitory computer-readable storage medium of claim 15 , wherein the data state metric is at least one of: raw bit error rate or a distance to an optimal valley associated with a shifted threshold voltage distribution.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Kaynak Mustafa N
• Parthasarathy Sivagnanam
• Luo Xiangang
• Feeley Peter
• Batutis Devin M
• Wu Jiangang
• Ratnam Sampath K
• Nowell Shane
• Schuh Karl D

Classifications

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C29/021

  in voltage or current generators · CPC title