Managing error-handling flows in memory devices

Patent metadata

Field	Value
Publication number	US-12229000-B2
Application number	US-202318207525-A
Country	US
Kind code	B2
Filing date	Jun 8, 2023
Priority date	Mar 30, 2021
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is assigned to a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;
determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and
performing the error-handling operation to recover the data.

2. The system of claim 1 , wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin.

3. The system of claim 1 , wherein the operations further comprise:
maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

4. The system of claim 1 , wherein the operations further comprise:
adjusting an order of a set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations.

5. The system of claim 4 , wherein the operations further comprise:
in response to a current error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the current error-handling operation.

6. The system of claim 4 , wherein the predetermined position is set during at least one of programming or calibration of the memory device.

7. The system of claim 4 , wherein the operations further comprise:
performing one or more error-handling operations of the set of error handling operations to recover the data in the adjusted order until data associated to the read error is recovered.

8. A method, comprising:
detecting a read error with respect to data residing in a first block of a memory device, wherein the first block is assigned to with a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;
determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and
performing the error-handling operation to recover the data.

9. The method of claim 8 , wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin.

10. The method of claim 8 , further comprising:
maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

11. The method of claim 8 , further comprising:
adjusting an order of a set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations.

12. The method of claim 11 , further comprising:
in response to a current error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the current error-handling operation.

13. The method of claim 11 , wherein the predetermined position is set during at least one of programming or calibration of the memory device.

14. The method of claim 11 , further comprising:
performing one or more error-handling operations of the set of error handling operations to recover the data in the adjusted order until data associated to the read error is recovered.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operatively coupled to a memory, performs operations comprising:
detecting a read error with respect to data residing in a first block of a memory device, wherein the first block is assigned to with a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;
determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and
performing the error-handling operation to recover the data.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin.

17. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise:
maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

18. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise:
adjusting an order of a set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the operations further comprise:
in response to a current error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the current error-handling operation.

20. The non-transitory computer-readable storage medium of claim 18 , wherein the operations further comprise:
performing one or more error-handling operations of the set of error handling operations to recover the data in the adjusted order until data associated to the read error is recovered.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Nowell Shane
• Kaynak Mustafa N
• Ratnam Sampath K
• Feeley Peter
• Parthasarathy Sivagnanam
• Batutis Devin M
• Luo Xiangang

Classifications

• G06F11/0727 Primary

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F13/1668

  Details of memory controller · CPC title