Resequencing data programmed to multiple level memory cells at a memory sub-system

Patent metadata

Field	Value
Publication number	US-12561080-B2
Application number	US-202217715799-A
Country	US
Kind code	B2
Filing date	Apr 7, 2022
Priority date	Dec 22, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A first set of host data items are programmed to first memory pages residing at a first region of a memory sub-system. A second set of host data items are programmed to second memory pages residing at the first region. A determination is made that a sequence at which the first set of host data items and the second set of host data items are programmed does not correspond to a target sequence associated with the memory sub-system. One or more of the first set of host data items are copied from one or more first memory pages to a second region of the memory sub-system that is allocated to store host data items initially programmed to first memory pages at the memory sub-system. One or more of the second set of host data items are copied from one or more second memory pages to a third region of the memory sub-system to store host data items that are programmed to second pages at the memory sub-system. A sequence of the copied one or more of the first set of host data items at the second region and the copied one or more of the second set of host data items at the third region correspond to the target sequence.

First claim

What is claimed is:

1 . A method comprising:
programming a first set of host data items to first memory pages residing at a first region of a memory sub-system; programming a second set of host data items to second memory pages residing at the first region; determining that a first sequence at which the first set of host data items and the second set of host data items are programmed does not correspond to a target sequence associated with the memory sub-system, wherein the target sequence is based on a numerical order of logical memory addresses of the first and second sets of host data items; copying one or more of the first set of host data items from one or more first memory pages to a second region of the memory sub-system allocated to store host data items that were initially programmed to first memory pages at the memory sub-system, wherein the second region is configured for lower memory pages, wherein the lower memory pages utilize a lower bit and are programmed using a first programming voltage; and copying one or more of the second set of host data items from one or more second memory pages to a third region of the memory sub-system allocated to store host data items that are programmed to second pages at the memory sub-system, wherein the third region is configured for higher memory pages, wherein the higher memory pages utilize an upper bit or an extra bit and are programmed using a second programming voltage that is higher than the first programming voltage, and wherein a second sequence of the copied one or more of the first set of host data items at the second region and the copied one or more of the second set of host data items at the third region correspond to the target sequence.

2 . The method of claim 1 , wherein the target sequence minimizes data fragmentation of host data across one or more memory devices of the memory sub-system.

3 . The method of claim 1 , wherein at least one of the one or more of the first set of host data items or the one or more of the second set of host data items are copied from the first region responsive to detecting an idle time period associated with incoming host data traffic.

4 . The method of claim 1 , wherein the first region of the memory sub-system and the second region of the memory sub-system correspond to regions associated with storing data items that are subject to a media management operation.

5 . The method of claim 1 , wherein the first memory pages correspond to a first memory page level of a first set of memory cells residing at the first region and the second memory pages to one or more second memory page levels of the first set of memory cells.

6 . The method of claim 5 , wherein the second memory pages correspond to at least one of upper memory pages or extra memory pages residing at the first region.

7 . The method of claim 1 , wherein the first region, the second region, and the third region of the memory sub-system each include at least one of a multi-level memory cell, a triple-level memory cell, or a quad-level memory cell.

8 . A system comprising:
one or more memory devices; and a processing device coupled to the one or more memory devices, wherein the processing device is to perform operations comprising: programming a first set of host data items to first memory pages associated with a first set of memory cells residing at the one or more memory devices; programming a second set of host data items to second memory pages associated with the first set of memory cells residing at the one or more memory devices; detecting that a host data item of at least one of the first set of host data items programmed to a first memory page associated with the first set of memory cells or the second set of host data items programmed to a second memory page associated with the first set or memory cells is invalid; and performing a memory management operation at the one or more memory devices to remove an invalid data item from the one or more memory devices, wherein performing the memory management operation comprises at least one of: copying valid host data items of the first set of host data items from the first memory pages to a second set of memory cells allocated to store host data items that were initially programmed to first memory pages at the one or more memory devices in accordance with a target sequence, wherein the target sequence is based on a numerical order of logical memory addresses of the first and second sets of host data items, and wherein the second set of memory cells reside at a first region that is configured for lower memory pages, the lower memory pages utilizing a lower bit and are programmed using a first programming voltage, or copying valid host data items of the second set of host data items from the second memory page to a third set of memory cells allocated to store host data items that were initially programmed to second memory pages at the one or more memory devices in accordance with the target sequence, wherein the third set of memory cells reside at a second region that is configured for higher memory pages, the higher memory pages utilizing an upper bit or an extra bit and are programmed using a second programming voltage that is higher than the first programming voltage.

9 . The system of claim 8 , wherein the operations further comprise:
maintaining a first cursor configured to indicate memory cells that are available to store data programmed to the first memory pages at the one or more memory devices and a second cursor configured to indicate memory cells that are available to store data programmed to the second memory pages at the one or more memory devices, wherein the first cursor indicates the second set of memory cells and the second cursor indicates the third set of memory cells.

10 . The system of claim 9 , wherein at least one of the first cursor or the second cursor is a garbage collection cursor.

11 . The system of claim 8 , wherein a first sequence at which at least one of the first set of host data items or the second set of host data items are programmed to the one or more memory devices does not correspond to the target sequence, and wherein a second sequence at which at least one of the valid host data items of the first set of host data items are copied to the second set of memory cells or the valid host data items of the second set of host data items are copied to the third set of memory cells corresponds to the target sequence.

12 . The system of claim 8 , wherein the first memory pages correspond to a first memory page level associated with the first set of memory cells and the second memory pages correspond to one or more second memory pages levels associated with the first set of memory cells.

13 . The system of claim 12 , wherein the second memory pages correspond to at least one of upper memory pages or extra memory pages associated with the first set of memory cells.

14 . The system of claim 8 , wherein the first set of memory cells, the second set of memory cells, and the third set of memory cells each include at least one of a multi-level memory cell, a triple-level memory cell, or a quad-level memory cell.

15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
programming a first set of host data items to first memory pages residing at a first region of a memory sub-system; programming a second set of host data items to second memory pages residing at the first region; determining that a first sequence at which the first set of

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Malshe Ashutosh
• Feeley Peter
• Parry Jonathan S
• Goda Akira
• Mcneil Jeffrey S

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F12/0253

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title