Voltage bin calibration based on a voltage distribution reference voltage

Patent metadata

Field	Value
Publication number	US-12393363-B2
Application number	US-202418616006-A
Country	US
Kind code	B2
Filing date	Mar 25, 2024
Priority date	Mar 16, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

First claim

What is claimed is:

1. A method comprising:
determining an amount of voltage shift for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells; and
associating the block family with a first voltage bin or a second voltage bin based on the determined amount of voltage shift, wherein the first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

2. The method of claim 1 , wherein the subsequent reference value is a current reference value and the initial reference value is associated with a memory voltage distribution for the one or more memory cells when data was written to the one or more memory cells.

3. The method of claim 1 , wherein determining the amount of voltage shift for the one or more memory cells comprises:
measuring a current memory access voltage distribution for the one or more memory cells, wherein the subsequent reference value is determined based on the measured current memory access voltage distribution.

4. The method of claim 3 , wherein the current memory access voltage distribution corresponds to at least one of a read voltage distribution or a write voltage distribution.

5. The method of claim 1 , wherein the block family is associated with the first voltage bin prior to determining the amount of voltage shift for the one or more memory cells.

6. The method of claim 5 , wherein associating the block family with the first voltage bin or the second voltage bin based on the determined amount of voltage shift comprises:
determining whether the determined amount of voltage shift satisfies a voltage shift criterion; and
responsive to determining that the determined amount of voltage shift satisfies the voltage shift criterion, associating the block family with the second voltage bin.

7. The method of claim 1 , wherein the initial reference value corresponds to a prior memory access voltage associated with the at least one of the one or more memory cells, wherein the at least one of the one or more memory cells was programmed at a faster rate than each other memory cell of the one or more memory cells.

8. The method of claim 7 , wherein determining the amount of voltage shift for the one or more memory cells comprises:
obtaining a current memory access voltage for the at least one of the one or more memory cells; and
determining a voltage difference between the current memory access voltage for the at least one of the one or more memory cells and the prior memory access voltage for the at least one of the one or more memory cells.

9. The method of claim 7 , wherein determining the amount of voltage shift for the one or more memory cells comprises:
determining a current memory access voltage associated with at least one of the one or more memory cells that is associated with a particular quantile of a current memory access voltage distribution; and
determining a difference between the current memory access voltage associated with the at least one of the one or more memory cells and a prior memory access voltage associated with another memory cell associated with the particular quantile of a prior memory access voltage distribution.

10. A system comprising:
a memory device; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
determining an amount of voltage shift for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells; and
associating the block family with a first voltage bin or a second voltage bin based on the determined amount of voltage shift, wherein the first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

11. The system of claim 10 , wherein the subsequent reference value is a current reference value and the initial reference value is associated with a memory voltage distribution for the one or more memory cells when data was written to the one or more memory cells.

12. The system of claim 10 , wherein determining the amount of voltage shift for the one or more memory cells comprises:
measuring a current memory access voltage distribution for the one or more memory cells, wherein the subsequent reference value is determined based on the measured current memory access voltage distribution.

13. The system of claim 12 , wherein the current memory access voltage distribution corresponds to at least one of a read voltage distribution or a write voltage distribution.

14. The system of claim 10 , wherein the block family is associated with the first voltage bin prior to determining the amount of voltage shift for the one or more memory cells.

15. The system of claim 14 , wherein associating the block family with the first voltage bin or the second voltage bin based on the determined amount of voltage shift comprises:
determining whether the determined amount of voltage shift satisfies a voltage shift criterion; and
responsive to determining that the determined amount of voltage shift satisfies the voltage shift criterion, associating the block family with the second voltage bin.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
determining an amount of voltage shift for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells; and
associating the block family with a first voltage bin or a second voltage bin based on the determined amount of voltage shift, wherein the first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the subsequent reference value is a current reference value and the initial reference value is associated with a memory voltage distribution for the one or more memory cells when data was written to the one or more memory cells.

18. The non-transitory computer-readable storage medium of claim 16 , wherein determining the amount of voltage shift for the one or more memory cells comprises:
measuring a current memory access voltage distribution for the one or more memory cells, wherein the subsequent reference value is determined based on the measured current memory access voltage distribution.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the current memory access voltage distribution corresponds to at least one of a read voltage distribution or a write voltage distribution.

20. The non-transitory computer-readable storage medium of claim 16 , wherein the block family is associated with the first voltage bin prior to determining the amount of voltage shift for the one or more memory cells.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Batutis Devin M
• Luo Xiangang
• Kaynak Mustafa N
• Feeley Peter
• Parthasarathy Sivagnanam
• Ratnam Sampath
• Nowell Shane

Classifications

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title