Memory device with dynamic cache management

Patent metadata

Field	Value
Publication number	US-12216573-B2
Application number	US-202318395363-A
Country	US
Kind code	B2
Filing date	Dec 22, 2023
Priority date	Aug 31, 2017
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

First claim

We claim:

1. An apparatus, comprising:
a memory array including memory cells; and
a controller coupled to the memory array, the controller configured to:
designate a portion of the memory cells as cache memory;
designate a storage mode for the cache memory based on a data storage measure,
wherein the storage mode is for dynamically configuring the cache memory to store a number of bits less per cell than a maximum capacity of bits per cell.

2. The apparatus of claim 1 , wherein the data storage measure is correlated with valid data stored in the cache memory.

3. The apparatus of claim 2 , wherein the valid data is associated with a garbage collection (GC) process.

4. The apparatus of claim 3 , wherein the controller is configured to designate single-level cell (SLC) mode for the storage mode when the valid data associated with the GC process is below a decision threshold.

5. The apparatus of claim 3 wherein the controller is configured to designate an extra-level cell (XLC) mode for the storage mode when the valid data is not less than a decision threshold.

6. The apparatus of claim 3 , wherein:
the cache memory is associated with a GC source block; and
the controller is further configured to:
calculate the data storage measure for the GC source block for representing an amount of the valid data within the GC source block; and
designate the cache memory to operate in SLC mode based on comparing the data storage measure to a decision threshold.

7. The apparatus of claim 6 , wherein the decision threshold corresponds to operating the cache memory in the SLC mode when the valid data within the source block is less than 25% of a total capacity of the source block.

8. The apparatus of claim 1 wherein the cache memory is indicated by a host cursor for the subsequent or upcoming data writes.

9. The apparatus of claim 1 wherein the cache memory is indicated by a GC cursor for the subsequent or upcoming data writes.

10. The apparatus of claim 1 wherein the controller is further configured to:
according to the data storage measure, determine a low logic saturation state for the memory array; and
based on the low logic saturation state, designate SLC mode for the storage mode for upcoming data writes.

11. The apparatus of claim 1 wherein the controller is configured to designate the storage mode as SLC mode under steady-state.

12. The apparatus of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of an amount of the data previously written in the SLC mode.

13. The apparatus of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of a data desirability measure associated with a performance model for characterizing the previously stored data.

14. A method of operating an apparatus that includes a controller and memory array having memory cells, the method comprising:
designating a portion of the memory cells as cache memory;
designating a storage mode for the cache memory based on a data storage measure,
wherein the storage mode is for dynamically configuring the cache memory to store a number of bits per cell less than the corresponding maximum storage capacity.

15. The method of claim 14 , wherein the data storage measure is correlated with valid data stored in the cache memory.

16. The method of claim 15 , wherein the valid data is identified during a GC process.

17. The method of claim 14 , wherein the cache memory is indicated by a GC cursor for a subsequent or upcoming data writes.

18. The method of claim 14 , wherein designating the storage mode includes designating a SLC mode for the storage mode when the valid data is less than a decision threshold.

19. The method of claim 18 , wherein designating the SLC mode includes designating the SLC mode regardless of an amount of the data previously written in the SLC mode, regardless of a data desirability measure associated with a performance model for characterizing the previously stored data, or a combination thereof.

20. A memory system, comprising:
a host device; and
a memory device coupled to the host device and configured to store data and provide access to the data for the host device, the memory device further configured to:
designate a portion of local storage capacity as cache memory;
designate a storage mode for the cache memory based on a data storage measure,
wherein the storage mode is for dynamically configuring the cache memory to store a number of bits less per cell than a maximum capacity of bits per cell.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Feeley Peter
• Malshe Ashutosh
• Hubbard Daniel J
• Hale Christopher S
• Brandt Kevin R
• Ratnam Sampath K
• Li Yun
• Hamilton Marc S

Classifications

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title