Bus interface optimization by selecting bit-lanes having best performance margins

Patent metadata

Field	Value
Publication number	US-9459982-B2
Application number	US-201414299319-A
Country	US
Kind code	B2
Filing date	Jun 9, 2014
Priority date	Jan 6, 2014
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.

First claim

What is claimed is:

1. A method of operating a bus interface, the method comprising:
measuring performance of the bus interface at a first operating frequency of the bus interface;
allocating bit-lanes for which performance margins lie closest to specified minimum performance margins at the first operating frequency as spare bit-lanes and the remainder of the bit-lanes of the bus interface as operational bit-lanes, wherein at a center of a data window the operational bit-lanes individually represent bits of a value communicated in parallel over the bus interface at the first operating frequency;
subsequent to the measuring the performance, operating the bus interface using the operational bit-lanes; and
responsive to detecting a failure of one of the operational bit-lanes, allocating a replacement bit-lane from the spare bit-lanes.

2. The method of claim 1 , wherein the first operating frequency of the bus interface is an operating frequency for which performance margins specified for the bus interface are violated for a number of the bit-lanes, wherein the allocating allocates the bit-lanes for which performance margins are violated at the first operating frequency as spare bit-lanes and the remainder of the bit-lanes of the bus interface as operational bit-lanes, and wherein the method further comprises responsive to allocating the replacement bit-lane, operating the bus interface at an operating frequency less than the first operating frequency for which the replacement bit-lane does not violate the performance margins specified for the bus interface.

3. The method of claim 2 , wherein the subsequently operating operates the bus interface at the first operating frequency.

4. The method of claim 2 , further comprising repeating the measuring while increasing the operating frequency of the bus interface until the performance margins are violated for the number of the bit-lanes when the operating frequency has been increased to the first operating frequency.

5. The method of claim 2 , wherein the measuring comprises:
first measuring the performance of the bus interface with correction circuitry disabled at a nominal operating frequency to determine worst-case performance margins for the bit-lanes, wherein the allocating allocates any bit-lanes that fails the worst-case performance margins as spare bit-lanes;
second measuring the performance of the bus interface with the correction circuitry enabled to determine corrected performance margins for the bit-lanes, wherein the allocating allocates any bit-lanes for which the corrected performance margins violate the specified performance margins as spare bit-lanes; and
repeating the second measuring while increasing the operating frequency of the bus interface until the number of bit-lanes not allocated as spares is equal to the number of bit-lanes required for operation of the bus interface.

6. The method of claim 2 , further comprising:
evaluating the performance for standardized workloads of an interface design having the same characteristic as the bus interface;
storing an initial operating frequency and set of operating bit-lanes for the bus interface, wherein the allocating initially allocates the set of operating bit-lanes as the operational bit-lanes;
initializing the bus interface at the initial operating frequency, wherein the measuring is performed subsequent to the initializing during operation;
increasing the operating frequency of the bus interface during operation; and
responsive to the measuring determining the performance margins are violated for an operational bit-lane, reducing the operating frequency of the bus interface.

7. The method of claim 6 , wherein the reducing the operating frequency of the bus interface restores the operating frequency of the bus interface to the initial operating frequency, and wherein the method further comprises performing a calibration of the bus interface in response to restoring the operating frequency of the bus interface to the initial operating frequency.

8. A computer system comprising a processor for executing program instructions coupled to a memory for storing the program instructions, wherein the program instructions are program instructions for configuring a bus interface, and wherein the program instructions comprise:
program instructions initiating measurement of performance of the bus interface at a first operating frequency of the bus interface;
program instructions for allocating the bit-lanes for which performance margins lie closest to specified minimum performance margins at the first operating frequency as spare-bit lanes and the remainder of the bit-lanes of the bus interface as operational bit-lanes, wherein at a center of a data window the operational bit-lanes individually represent bits of a value communicated in parallel over the bus interface at the first operating frequency;
program instructions that subsequent to the measuring the performance, configure the bus interface for operation using the operational bit-lanes; and
program instructions that, responsive to detection of a failure of one of the operational bit-lanes, allocate a replacement bit-lane from the spare bit-lanes.

9. The computer system of claim 8 , wherein the first operating frequency of the bus interface is an operating frequency for which performance margins specified for the bus interface are violated for a number of the bit-lanes, wherein the program instructions for allocating allocate the bit-lanes for which performance margins are violated at the first operating frequency as spare-bit lanes and the remainder of the bit-lanes of the bus interface as operational bit-lanes, and wherein the program instructions further comprise program instructions that, responsive to allocating the replacement bit-lane, configure the bus interface for operation at an operating frequency less than the first operating frequency for which the replacement bit-lane does not violate the performance margins specified for the bus interface.

10. The computer system of claim 9 , wherein the program instructions that configure the bus interface configure the bus interface for operation at the first operating frequency.

11. The computer system of claim 9 , further comprising program instructions for repeatedly initiating the measurement of the performance of the bus interface while increasing the operating frequency of the bus interface until the performance margins are violated for the number of the bit-lanes when the operating frequency has been increased to the first operating frequency.

12. The computer system of claim 9 , wherein the program instructions for initiating the measurement comprise:
program instructions for first initiating measurement of the performance of the bus interface with correction circuitry disabled at a nominal operating frequency to determine worst-case performance margins for the bit-lanes, wherein the program instructions for allocating allocate any bit-lanes that fails the worst-case performance margins as spare bit-lanes;
program instructions for second initiating measurement of the performance of the bus interface with the correction circuitry enabled to determine corrected performance margins for the bit-lanes, wherein the program instructions for allocating allocate any bit-lanes for which the corrected performance margins violate the specified performance margins as spare bit-lanes; and
program instructions for repeating the second initiating the measurement while increasing the operating frequency of the bus interface until the number of bit-lanes not allocated as spares is equal to the number of bit-lanes required for operation of the bus interface.

Assignees

• IBM

Inventors

• Dreps Daniel Mark
• Ferraiolo Frank D
• Haridass Anand
• Jayaraman Prasanna

Classifications

• G06F11/2007 Primary

  using redundant communication media · CPC title

• G06F11/3409

  for performance assessment · CPC title

• G06F11/34

  Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation {; Recording or statistical evaluation of user activity, e.g. usability assessment} · CPC title

• G06F11/2002

  where interconnections or communication control functionality are redundant (flexible arrangements for bus networks involving redundancy H04L12/40176) · CPC title

• G06F11/3041 Primary

  where the computing system component is an input/output interface (interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00) · CPC title