Multi-phase clock generation circuit with digital calibration

Patent metadata

Field	Value
Publication number	US-12500581-B2
Application number	US-202318345046-A
Country	US
Kind code	B2
Filing date	Jun 30, 2023
Priority date	Jun 30, 2023
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A power saving improvement in an injection locked oscillator (ILO) used is described. The ILO circuitry comprises a feedback path to provide a finecal (M-bit fine calibration signal). The feedback path need not be active at all times; only when an event occurs that requires the feedback path to update the value of the finecal signal. A monitor is provided to sense the occurrence of such event which may be, for examples, an end of a time period or a predetermined change in temperature. When the event occurs, the feedback path is activated to update the value of the finecal signal.

First claim

What is claimed is:

1 . A clock generation circuit comprising:
an output at CMOS (complementary metal oxide semiconductor) levels to high-speed receivers; an injection locked oscillator (ILO) further comprising a coarse tuning input directly in the ILO and an M-bit fine calibration (finecal) signal input to the ILO; and a feedback path from the output to provide the finecal signal having a controller, the controller being turned off until an event turns it on,
wherein the controller includes a random logic module (RLM).

2 . The clock generation circuit of claim 1 , further comprising a monitor to detect the event.

3 . The clock generation circuit of claim 2 , wherein the event is an end of a predetermined period of time.

4 . The clock generation circuit of claim 2 , wherein the event is a detection of a predetermined change in temperature.

5 . A method to set a finecal (M-bit fine calibration) signal in an injection locked oscillator (ILO) comprising:
setting all bits in finecal to 0; enabling a feedback loop in the ILO; setting a polarity signal to 0, the polarity signal used in circuitry to mitigate effects of FET (field effect transistors) mismatch in a comparator; waiting “X” cycles, where “X” is a user-defined value to let the ILO adapt to the new finecal value; checking the comparator, if “1” a coarse tuning error has occurred and the method ends; if the comparator is “0”, incrementing finecal by increasing the number of “1” bits in the M-bit fine calibration signal by one and waiting “X” cycles until comparator is “1”; storing the current value of finecal as a first result; setting finecal to “1” by making all bits in the M-bit fine calibration signal “1”; setting the polarity signal to “1”; waiting “X” cycles; checking comparator, if “0” there is an error in the coarse tuning signal and the method ends; if comparator is “1”, decrementing finecal (changing a bit in finecal from “1” to “0”) until comparator is “0”; setting a second result equal to the current value of finecal; setting finecal equal to (first result+second result)/2; and disabling the feedback loop.

6 . A method of reducing jitter and improving phase response in a clock generation system having an injection locked oscillator (ILO) which uses an N-bit coarse tuning directly in the ILO and an M-bit fine calibration signal, the method comprising:
turning on a feedback loop in the clock generation system during a calibration period in which receiver circuitry is not using an output of the ILO,
wherein the clock generation system includes a controller includes a random logic module (RLM);
determining a correct value for the M-bit fine calibration signal; and turning off the feedback loop in the clock generation system until a monitor causes another calibration time.

7 . The method of claim 6 , jitter being inherently reduced by absence of changes in the M-bit fine calibration signal while the feedback loop is turned off.

8 . The method of claim 6 , phase response being inherently improved by absence of changes in the M-bit fine calibration signal while the feedback loop is turned off.

9 . The method of claim 6 , including saving power when the feedback loop is turned off.

10 . The clock generation circuit of claim 1 , wherein the controller is provided in the feedback path from the output to provide the finecal signal.

11 . The clock generation circuit of claim 10 , wherein the controller in the feedback path from the output to provide the finecal signal further comprises a low pass filter.

12 . The clock generation circuit of claim 11 , wherein the controller in the feedback path from the output to provide the finecal signal further comprises a phase detector.

13 . The clock generation circuit of claim 12 , wherein the controller in the feedback path from the output to provide the finecal signal further comprises a comparator positioned between the low pass filter and the RLM.

14 . The method of claim 6 , wherein the controller further includes a low pass filter.

15 . The method of claim 14 , wherein the controller further includes a phase detector.

16 . The method of claim 15 , wherein the controller includes a comparator positioned between the low pass filter and the RLM.

Assignees

• IBM

Inventors

• Friend David M
• Dreps Daniel Mark
• Yilma Dereje
• Wiedemeier Glen A
• You Yang

Classifications

• H03K5/24

  the characteristic being amplitude · CPC title

• H03K5/1252 Primary

  Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) · CPC title

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title