Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output

Patent metadata

Field	Value
Publication number	US-11804828-B2
Application number	US-202217676924-A
Country	US
Kind code	B2
Filing date	Feb 22, 2022
Priority date	Feb 22, 2022
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit comprises:
a main path including a main multiplexer (MUX) having a first input to receive a pre-defined data pattern and a first output connected to a main driver input of a main driver circuit;
a replica path including a replica MUX having a second input to receive the pre-defined data pattern and a second output connected to a replica driver input of a replica driver circuit;
a selection MUX connected to the main path to receive a first main driver output and a second main driver output, and connected to the replica path to receive a first replica driver output and a second replica driver output;
operating the selection MUX, during a period for the chip initialization, to select the first and second main driver outputs as inputs to the selection MUX;

inputting the pre-defined data pattern to the main path;
comparing the first main driver output having a first portion of the pre-defined data pattern with the second main driver output having a second portion of the pre-defined data pattern to determine duty cycle issue; and
generating an adjustment vector based on the determined duty cycle issue.

2. The computer-implemented method of claim 1 , further comprising:
inputting the adjustment vector to a clock circuit to adjust a duty cycle of a clock signal for the DCC circuit.

3. The computer-implemented method of claim 1 , further comprising:
receiving, by the controller, a second indication of an expiration of the chip initialization period for the DCC circuit;
operating the selection MUX to select the first and second replica driver outputs as inputs to the selection MUX;
inputting the pre-defined data pattern to the replica path;
comparing first replica driver output having a first portion of the pre-defined data pattern with the second replica driver output having a second portion of the pre-defined data pattern to determine a path mismatch issue; and
generating a second adjustment vector based on the determined path mismatch issue.

4. The computer-implemented method of claim 3 , further comprising:
inputting the second adjustment vector to the comparator to adjust for the path mismatch issue.

5. The computer-implemented method of claim 3 , further comprising:
inputting the second adjustment vector to the replica driver to adjust for the path mismatch issue.

6. The computer-implemented method of claim 1 , wherein an output of the selection MUX is connected to a low pass filter.

7. The computer-implemented method of claim 1 , wherein the main MUX is a serializer for a serializer/deserializer (SerDes) system.

8. A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
receiving an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit comprises:
a main path including a main multiplexer (MUX) having a first input to receive a pre-defined data pattern and a first output connected to a main driver input of a main driver circuit;
a replica path including a replica MUX having a second input to receive the pre-defined data pattern and a second output connected to a replica driver input of a replica driver circuit;
a selection MUX connected to the main path to receive a first main driver output and a second main driver output, and connected to the replica path to receive a first replica driver output and a second replica driver output;
operating the selection MUX, during a period for the chip initialization, to select the first and second main driver outputs as inputs to the selection MUX;
inputting the pre-defined data pattern to the main path;
comparing the first main driver output having a first portion of the pre-defined data pattern with the second main driver output having a second portion of the pre-defined data pattern to determine a duty cycle issue; and
generating an adjustment vector based on the determined duty cycle issue.

9. The system of claim 8 , wherein the operations further comprise:
inputting the adjustment vector to a clock circuit to adjust a duty cycle of a clock signal for DCC circuit.

10. The system of claim 8 , wherein the operations further comprise:
receiving, by the controller, a second indication of an expiration of the chip initialization period for the DCC circuit;
operating the selection MUX to select the first and second replica driver outputs as inputs to the selection MUX;
inputting the pre-defined data pattern to the replica path; and
comparing first replica driver output having a first portion of the pre-defined data pattern with the second replica driver output having a second portion of the pre-defined data pattern to determine a path mismatch issue; and
generating a second adjustment vector based on the determined path mismatch issue.

11. The system of claim 10 , wherein the operations further comprise:
inputting the second adjustment vector to the comparator to adjust for the path mismatch issue.

12. The system of claim 10 , further comprising:
inputting the second adjustment vector to the replica driver to adjust for the path mismatch issue.

13. The system of claim 8 , wherein an output of the selection MUX is connected to a low pass filter.

14. The system of claim 8 , wherein the main MUX is a serializer for a serializer/deserializer (SERDES) system.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit comprises:
a main path including a main multiplexer (MUX) having a first input to receive a pre-defined data pattern and a first output connected to a main driver input of a main driver circuit;
a replica path including a replica MUX having a second input to receive the pre-defined data pattern and a second output connected to a replica driver input of a replica driver circuit;
a selection MUX connected to the main path and the replica path;
operating the selection MUX, during a period for the chip initialization, to select the first and second main driver outputs as inputs to the selection MUX;
inputting the pre-defined data pattern to the main path;
comparing the first main driver output having a first portion of the pre-defined data pattern with the second main driver output having a second portion of the pre-defined data pattern to determine duty cycle issue; and
generating an adjustment vector based on the determined duty cycle issue.

16. The computer program product of claim 15 , wherein the operations further comprise:
inputting the adjustment vector to a clock circuit to adjust a duty cycle of a clock signal for DCC circuit.

17. The computer program product of claim 15 , wherein the operations further comprise:
receiving, by the controller, a second indication of an expiration of the chip initialization period for the DCC circuit;
operating the selection MUX to select the first and second replica driver outputs as inputs to the selection MUX

Assignees

• IBM

Inventors

• Qi Jieming
• Dreps Daniel Mark
• Wiedemeier Glen A
• Lukes Eric John
• Cox Carrie Ellen
• Dickson Timothy O

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title