System interconnect dynamic scaling handshake using spare bit-lane

Patent metadata

Field	Value
Publication number	US-9558139-B2
Application number	US-201414462278-A
Country	US
Kind code	B2
Filing date	Aug 18, 2014
Priority date	Aug 18, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.

First claim

What is claimed is:

1. A communications interface for connecting processing units within a computer system, the interface comprising:
a first physical link layer within a first one of the processing units and comprising a first transceiver and a first control circuit;
a second physical link layer within a second one of the processing units and comprising a second transceiver and a second control circuit;
a plurality of bit-lanes connecting the first transceiver of the first physical link layer transceiver and the second transceiver of the second physical link layer, wherein the first control circuit changes at least one of a first active width or a first operating frequency of first transceiver to at least one of a second active width or a second operating frequency and communicates an indication of the at least one of the second active width or the second operating frequency to the second control circuit over a spare bit lane of the interface, wherein the spare bit lane is a lane that is not in use for the communicating of data between the first physical link layer and the second physical link layer, and wherein the second control circuit receives the indication, and in response, changes at least one of an active width or an operating frequency of the second transceiver to the at least one of the second width or the second operating frequency and communicates an acknowledgement to the first control circuit that indicates that the second transceiver is operating with the at least one of the second width or the second operating frequency as changed in response to receiving the indication, wherein subsequent to the second control circuit changing the second active width of the interface, the interface has a current active width less than a maximum active width of the interface, whereby one or more bit-lanes are disabled, and wherein the second control circuit uses the one or more disabled lanes of the interface to communicate the acknowledgement, whereby the indication is communicated over the spare bit-lane, but the acknowledgement is not communicated over the spare bit-lane.

2. The communications interface of claim 1 , wherein the first control circuit communicates the indication over a single spare bit-lane of the interface, and wherein the second control circuit communicates the acknowledgement over the same single spare bit-lane by the first control circuit and the second control circuit bi-directionally encoding the indication and the acknowledgement by time-division.

3. The communications interface of claim 2 , wherein the first control circuit transmits a first command code along with the indication to the second physical link layer, and wherein the second control circuit transmits a second acknowledgement code to the first physical link layer, whereby other information can be transmitted on the single spare bit-lane.

4. The communications interface of claim 1 , wherein the second control circuit determines whether or not the current active width of the interface is less than the maximum active width, wherein the second control circuit uses the one or more disabled lanes selectively in response to determining that the current active width of the interface is less than the maximum active width, and wherein the second control circuit uses the spare bit lane selectively in response to determining that current active width of the interface is not less than the maximum active width.

5. A computer system comprising:
a plurality of processing units;
a plurality of interfaces, wherein the plurality of interfaces comprise a pair of physical link layers including a transceiver and a control circuit, wherein the pair of physical link layers comprise and a plurality of bit-lanes connecting the transceivers of the pair of physical link layers, wherein a control circuit of a first one of the pair of physical link layers changes at least one of a first active width or a first operating frequency of corresponding transceiver to at least one of a second active width or a second operating frequency and communicates an indication of the at least one of the second active width or the second operating frequency to the control circuit of the other one of the pair of physical link layers over a spare bit lane of the interface, wherein the spare bit lane is a lane that is not in use for the communicating of data between the pair of physical link layers, and wherein the control circuit of the other one of the pair of physical link layers receives the indication, and in response, changes at least one of an active width or an operating frequency of the transceiver of the other one of the pair of physical link layers to the at least one of the second width or the second operating frequency and communicates an acknowledgement to the control circuit of the first one of the physical link layers that indicates that the transceiver of the other one of the physical link layers is operating with the at least one of the second width or the second operating frequency as changed in response to receiving the indication, wherein subsequent to the control circuit of the second one of the physical link layers changing the second active width of the interface, the interface has a current active width less than a maximum active width of the interface, whereby one or more bit-lanes are disabled, and wherein the control circuit of the second one of the physical link layers uses the one or more disabled lanes of the interface to communicate the acknowledgement, whereby the indication is communicated over the spare bit-lane, but the acknowledgement is not communicated over the spare bit-lane.

6. The computer system of claim 5 , wherein the control circuit of the first one of the physical link layers communicates the indication over a single spare bit-lane of the interface, and wherein the control circuit of the second one of the physical link layers communicates the acknowledgement over the same single spare bit-lane by the first control circuit and the second control circuit bi-directionally encoding the indication and the acknowledgement in a time-division multiplex.

7. The computer system of claim 6 , wherein the control circuit of the first one of the physical link layers transmits a first command code along with the indication to the second physical link layer, and wherein the control circuit of the second one of the physical link layers transmits a second acknowledgement code to the first one of the physical link layers, whereby other information can be transmitted on the single spare bit-lane.

8. The computer system of claim 5 , wherein the control circuit of the second one of the physical link layers determines whether or not the current active width of the interface is less than the maximum active width, wherein the control circuit of the second one of the physical link layers uses the one or more disabled lanes selectively in response to determining that the current active width of the interface is less than the maximum active width, and wherein the control circuit of the second one of the physical link layers uses the spare bit lane selectively in response to determining that current active width of the interface is not less than the maximum active width.

9. A communications interface for connecting processing units within a computer system, the interface comprising:
a first physical link layer within a first one of the processing units and comprising a first transceiver and a first control circuit;
a second physical link layer within a second one of the processing units and comprising a second transceiver and a second control circuit;
a plurality of bit-lanes connecting the first transceiver of the first physical link layer transceiver and the second transceiver of the second physical

Assignees

• IBM

Inventors

• Dreps Daniel Mark
• Ferraiolo Frank D
• Haridass Anand
• Jayaraman Prasanna

Classifications

• H04L69/321

  Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• H04L69/323

  in the physical layer [OSI layer 1] · CPC title