Power delivery network for CFET with buried power rails

Patent metadata

Field	Value
Publication number	US-12040271-B2
Application number	US-202318331651-A
Country	US
Kind code	B2
Filing date	Jun 8, 2023
Priority date	Oct 21, 2019
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

Aspects of the present disclosure provide a method for fabricating a semiconductor device. For example, the method can include forming a first power rail, forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source, forming an active device between the first power rail and the first power input structure, and forming a first middle-of-line rail with a plurality of layers. The first middle-of-line rail can be configured to deliver the electrical power from the first power input structure to the first power rail. The first power rail can provide the electrical power to the active device for operation. Topmost and bottommost ones of the layers of the first middle-of-line rail can be as high as and leveled with top and bottom surfaces of the active device, respectively.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a first power rail;
forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source;
forming an active device between the first power rail and the first power input structure; and
forming a first middle-of-line rail with a plurality of layers, the first middle-of-line rail being configured to deliver the electrical power from the first power input structure to the first power rail, the first power rail providing the electrical power to the active device for operation, topmost and bottommost ones of the layers of the first middle-of-line rail being as high as and leveled with top and bottom surfaces of the active device, respectively.

2. The method of claim 1 , further comprising:
forming a second power rail that is parallel with the first power rail;
forming a second power input structure for coupling with a second terminal of the power source to receive the electrical power from the power source; and
forming a second middle-of-line rail with a plurality of layers, the second middle-of-line rail being parallel with the first middle-of-line rail, and the first and second middle-of-line rails delivering the electrical power from the first and second input structures to the first and second power rails, the first and second power rails providing the electrical power to the active device for operation.

3. The method of claim 2 , wherein:
the first and second middle-of-line rails are perpendicular to the first and second power rails.

4. The method of claim 1 , wherein forming, the active device and the first middle-of-line rail further comprises:
forming a cell row of cell circuits that have a same height, the first middle-of-line rail including a section in a power tap cell that is disposed in the cell row, the power tap cell having a same cell height as the cell circuits.

5. The method of claim 4 , further comprising:
using at least one of the layers of the first middle-of-line rail to form connections within a cell circuit.

6. The method of claim 4 , further comprising:
forming multiple cell rows of cell circuits with power tap cells disposed in the multiple cell rows; and
forming the first middle-of-line rail using respective sections in the power tap cells.

7. The method of claim 6 , further comprising:
forming the power tap cells that are aligned in a column.

8. The method of claim 6 , wherein each section of the sections in the respective power tap cells is connected to the first power rail by at least a power via, and is connected to a metal rail by at least a contact.

9. The method of claim 1 , further comprising:
forming the active device having a second transistor and a first transistor that is disposed above the second transistor in a vertical direction that is parallel to a direction in that the active device is formed between the first power rail and the first power input structure.

10. The method of claim 9 , further comprising:
forming the first middle-of-line rail in a first layer that is used for forming local interconnects in the first transistor, a second layer that is used for forming local interconnects in the second transistor, and a strap layer that merges the first layer and the second layer.

11. The method of claim 10 , wherein the first layer is the topmost one of the layers, and the second layer is the bottommost one of the layers.

12. The method of claim 1 , further comprising:
forming an upper metal layer power delivery network between the first power input structure and the first middle-of-line rail, the upper metal layer power delivery network configured to deliver the electric power from the first power input structure to the first middle-of-line rail.

13. The method of claim 12 , further comprising:
forming first to seventh metal layers stacked over one another sequentially between the first power input structure and the first middle-of-line rail,
wherein the upper metal layer power delivery network includes metal wires that are formed in the first to seventh metal layers.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Devilliers Anton J

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title