Test structures connected with the lowest metallization levels in an interconnect structure
US-10796973-B2 · Oct 6, 2020 · US
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Chauhan Vikrant patents
Chauhan Vikrant is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chauhan Vikrant |
| Total patents | 21 |
| First publication | Jan 13, 2015 |
| Latest publication | Oct 6, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Test structure leveraging the lowest metallization level of an interconnect structure
US-10790204-B2 · Sep 29, 2020 · US
Test structures connected with the lowest metallization levels in an interconnect structure
US-2020152531-A1 · May 14, 2020 · US
Test structure leveraging the lowest metallization level of an interconnect structure
US-2020152530-A1 · May 14, 2020 · US
FDSOI semiconductor device with contact enhancement layer and method of manufacturing
US-10347543-B2 · Jul 9, 2019 · US
Three-dimensional pattern risk scoring
US-10311186-B2 · Jun 4, 2019 · US
Fdsoi semiconductor device with contact enhancement layer and method of manufacturing
US-2019148245-A1 · May 16, 2019 · US
Multi-directional self-aligned multiple patterning
US-10199270-B2 · Feb 5, 2019 · US
On-chip capacitors with floating islands
US-10147783-B2 · Dec 4, 2018 · US
Multi-directional self-aligned multiple patterning
US-2018342421-A1 · Nov 29, 2018 · US
Recent patents
Latest publications not already listed above.
On-chip capacitors with floating islands
US-2018269275-A1 · Sep 20, 2018 · US
Wafer level electrical test for optical proximity correction and/or etch bias
US-10078107-B2 · Sep 18, 2018 · US
Method for forming a shallow trench isolation structure using a nitride liner and a diffusionless anneal
US-2018040505-A1 · Feb 8, 2018 · US
Three-dimensional pattern risk scoring
US-2017293704-A1 · Oct 12, 2017 · US
Wafer level electrical test for optical proximity correction and/or etch bias
US-2017115337-A1 · Apr 27, 2017 · US
Multi-polygon constraint decomposition techniques for use in double patterning applications
US-9465907-B2 · Oct 11, 2016 · US
Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines
US-9412655-B1 · Aug 9, 2016 · US
Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines
US-2016225666-A1 · Aug 4, 2016 · US
Multi-polygon constraint decomposition techniques for use in double patterning applications
US-2016026748-A1 · Jan 28, 2016 · US
Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
US-2015050811-A1 · Feb 19, 2015 · US
Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
US-8932961-B2 · Jan 13, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Globalfoundries Inc | 20 |
| Globalfoundries Inc | 1 |
| Mehta Sohan | 1 |
| Chen Tong Qing | 1 |
| Chauhan Vikrant | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/0698 | 8 |
| H10P74/273 | 6 |
| H10W20/43 | 6 |
| H01L22/32 | 6 |
| H01L23/528 | 6 |