Test structure leveraging the lowest metallization level of an interconnect structure

Patent metadata

Field	Value
Publication number	US-10790204-B2
Application number	US-201816185696-A
Country	US
Kind code	B2
Filing date	Nov 9, 2018
Priority date	Nov 9, 2018
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

First claim

What is claimed is:

1. A structure comprising:
a first test pad;
a device-under-testing including one or more first source/drain regions;
a single metallization level arranged over the device-under-testing, the single metallization level including one or more first interconnect lines connected with the first test pad; and
one or more first contacts arranged between the single metallization level and the device-under-testing, the one or more first contacts directly connecting the one or more first interconnect lines with the one or more first source/drain regions,
wherein the one or more first interconnect lines of the single metallization level are arranged directly over the device-under-testing, and each of the one or more first interconnect lines is connected with one of the one or more first source/drain regions by only one of the one or more first contacts.

2. The structure of claim 1 wherein the single metallization level includes a transverse interconnect line arranged transverse to the one or more first interconnect lines, and each of the one or more first interconnect lines is directly connected with the transverse interconnect line.

3. The structure of claim 2 wherein the single metallization level includes one or more second interconnect lines extending from the transverse interconnect line to the first test pad.

4. The structure of claim 1 wherein the device-under-testing is a field-effect transistor.

5. The structure of claim 1 wherein the device-under-testing is a Kelvin field-effect transistor.

6. The structure of claim 5 wherein the first test pad is included among a group of seven test pads.

7. The structure of claim 1 wherein the one or more first interconnect lines include one or more mandrel lines and one or more non-mandrel lines.

8. The structure of claim 1 wherein the one or more first interconnect lines include a plurality of mandrel lines.

9. The structure of claim 1 wherein the one or more first interconnect lines include a plurality of non-mandrel lines.

10. A structure comprising:
a first test pad;
a second test pad;
a device-under-testing including one or more first source/drain regions, one or more second source/drain regions, and a gate structure arranged between the one or more first source/drain regions and the one or more second source/drain regions;
a single metallization level arranged over the device-under-testing, the single metallization level including one or more first interconnect lines connected with the first test pad and one or more second interconnect lines connected with the second test pad;
one or more first contacts arranged between the single metallization level and the device-under-testing, the one or more first contacts directly connecting the one or more first interconnect lines with the one or more first source/drain regions; and
one or more second contacts arranged between the single metallization level and the device-under-testing, the one or more second contacts directly connecting the one or more second interconnect lines with the one or more second source/drain regions.

11. The structure of claim 10 wherein each of the one or more second interconnect lines is connected with one of the one or more second source/drain regions by only one of the one or more second contacts.

12. The structure of claim 10 wherein each of the one or more first source/drain regions is a drain region, and each of the one or more second source/drain regions is a source region.

13. The structure of claim 10 wherein the first test pad and the second test pad are arranged in the single metallization level.

14. The structure of claim 10 wherein the one or more first interconnect lines include one or more first mandrel lines, and the one or more second interconnect lines include one or more second mandrel lines.

15. The structure of claim 10 wherein each of the one or more first interconnect lines is connected with one of the one or more first source/drain regions by only one of the one or more first contacts.

16. A method comprising:
forming a device-under-testing that includes one or more first source/drain regions, one or more second source/drain regions, and a gate structure arranged between the one or more first source/drain regions and the one or more second source/drain regions;
forming a first test pad;
forming a second test pad;
forming a single metallization level arranged over the device-under-testing, wherein the single metallization level include one or more first interconnect lines connected with the first test pad and one or more second interconnect lines connected with the second test pad; and
forming one or more first contacts and one or more second contacts arranged between the single metallization level and the device-under-testing,
wherein the one or more first contacts directly connect the one or more first interconnect lines with the one or more first source/drain regions, the one or more second contacts directly connect the one or more second interconnect lines with the one or more second source/drain regions, the one or more first interconnect lines of the single metallization level are arranged directly over the device-under-testing, and each of the one or more first interconnect lines is connected with one of the one or more first source/drain regions by only one of the one or more first contacts.

17. The method of claim 16 wherein the single metallization level includes a transverse interconnect line arranged transverse to the one or more first interconnect lines, and each of the one or more first interconnect lines is directly connected with the transverse interconnect line.

18. The method of claim 16 wherein each of the one or more second interconnect lines is connected with one of the one or more second source/drain regions by only one of the one or more second contacts.

Assignees

• Globalfoundries Inc

Inventors

• Yang Mankyu
• Vakada Vara Govindeswara Reddy
• Maciejewski Edward
• Greene Brian
• Ogino Atsushi
• Chauhan Vikrant
• Sengupta Prianka

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D30/00

  Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00) · CPC title