Wafer level electrical test for optical proximity correction and/or etch bias

Patent metadata

Field	Value
Publication number	US-10078107-B2
Application number	US-201514924439-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.

First claim

The invention claimed is:

1. A method, comprising:
providing at least one semiconductor die;
for each die, electrically connecting three reference resistors having a same designed resistance to a test structure to be tested in a circuit having a Wheatstone Bridge design, the circuit electrically coupled between an input and ground, wherein the test structure is an integrated circuit having a circuit design;
testing the circuit design of the integrated circuit, wherein the testing comprises:
applying a voltage across the input; and
measuring for an electrical characteristic difference between two midpoints of the circuit having the Wheatstone Bridge design, the electrical characteristic difference indicating a need for one or more corrective actions to be applied to the circuit design; and

applying the one or more corrective actions by modifying the circuit design to prevent the electrical characteristic difference.

2. The method of claim 1 , wherein the at least one semiconductor die comprises a plurality of dies on a semiconductor wafer, and wherein the applying and measuring are performed for each of the plurality of dies.

3. The method of claim 1 , wherein the electrical characteristic difference comprises a voltage difference.

4. The method of claim 1 , wherein the electrical characteristic difference comprises a resistance difference.

5. The method of claim 1 , wherein the reference resistors have a known optical proximity correction (OPC) bias, wherein each test structure has an unknown OPC bias, and wherein the one or more corrective actions achieves a desired resistance for the test structure.

6. The method of claim 5 , wherein the at least one semiconductor die comprises at least two semiconductor dies having different test structures with different OPC biases.

7. The method of claim 1 , wherein the at least one semiconductor die comprises at least two semiconductor dies having different test structures, and wherein the one or more corrective actions comprises altering an etch bias of the circuit design to substantially reduce or eliminate a difference in resistances of the different test structures.

8. The method of claim 1 , wherein the one or more corrective actions correct integrated circuit design at a pre-design stage of development.

9. The method of claim 1 , wherein the one or more corrective actions correct the circuit design at a design stage of development.

10. The method of claim 1 , wherein the one or more corrective actions correct the circuit design at a post-design stage of development.

11. The method of claim 1 , further comprising applying at least one of the one or more corrective actions to the circuit design of the integrated circuit.

Assignees

• Globalfoundries Inc

Inventors

• Bravo Jaime
• Chauhan Vikrant
• Smith Ryan Scott

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R31/2831 Primary

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/2607 Primary

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G01R31/2601

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title