Test structures connected with the lowest metallization levels in an interconnect structure

Patent metadata

Field	Value
Publication number	US-10796973-B2
Application number	US-201916425387-A
Country	US
Kind code	B2
Filing date	May 29, 2019
Priority date	Nov 9, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

First claim

What is claimed is:

1. A structure comprising:
a device-under-testing including one or more first source/drain regions;
a first metallization level arranged over the device-under-testing, the first metallization level including one or more first interconnect lines;
a contact level including one or more first contacts arranged between the first metallization level and the device-under-testing, the one or more first contacts directly connecting the one or more first interconnect lines with the one or more first source/drain regions;
a second metallization level arranged over the first metallization level, the second metallization level including a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad; and
a via level including a plurality of vertical interconnects connecting the one or more first interconnect lines with the one or more second interconnect lines,
wherein each of the one or more first interconnect lines is connected with one of the one or more first source/drain regions by only one of the one or more first contacts.

2. The structure of claim 1 wherein the first metallization level is one of a plurality of metallization levels in an interconnect structure, and the first metallization level is closest to the device-under-testing among the plurality of metallization levels.

3. The structure of claim 1 wherein the first metallization level and the second metallization level are included in an interconnect structure, and the first metallization level is closer to the device-under-testing than the second metallization level.

4. The structure of claim 1 wherein the first test pad is located in a buffer region of the second metallization level.

5. The structure of claim 1 wherein the one or more second interconnect lines include a section that is aligned transverse to the one or more first interconnect lines.

6. The structure of claim 1 wherein the one or more second interconnect lines include a first mandrel line connected with the one or more first interconnect lines and a second mandrel line connected with the first test pad, and the first mandrel line and the second mandrel line are arranged transverse to the one or more first interconnect lines.

7. The structure of claim 6 wherein the one or more first interconnect lines include a third mandrel line connecting the first mandrel line with the second mandrel line.

8. The structure of claim 1 wherein the one or more first interconnect lines are arranged directly over the device-under-testing.

9. The structure of claim 1 wherein the first metallization level includes a transverse interconnect line arranged transverse to the one or more first interconnect lines, and each of the one or more first interconnect lines is directly connected with the transverse interconnect line.

10. The structure of claim 1 wherein the device-under-testing includes one or more second source/drain regions and a gate structure arranged between the one or more first source/drain regions and the one or more second source/drain regions, and the second metallization level includes a second test pad and one or more third interconnect lines connecting the one or more first interconnect lines with the second test pad.

11. The structure of claim 1 wherein the device-under-testing is a field-effect transistor.

12. The structure of claim 1 wherein the device-under-testing is a Kelvin field-effect transistor.

13. A method comprising:
forming a device-under-testing that includes one or more first source/drain regions;
forming one or more contacts directly connected with the one or more first source/drain regions;
forming a first metallization level arranged over the device-under-testing, wherein the first metallization level includes one or more first interconnect lines, and the one or more contacts directly connect the one or more first interconnect lines with the one or more first source/drain regions;
forming a second metallization level arranged over the first metallization level, wherein the second metallization level includes a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad; and
forming a via level including a plurality of vertical interconnects connecting the one or more first interconnect lines with the one or more second interconnect lines,
wherein each of the one or more first interconnect lines is connected with one of the one or more first source/drain regions by only one of the one or more contacts.

14. The method of claim 13 wherein the first test pad is located in a buffer region of the second metallization level.

15. The method of claim 13 wherein the device-under-testing is a field-effect transistor.

16. The method of claim 13 wherein the device-under-testing is a Kelvin field-effect transistor.

17. The method of claim 13 wherein the device-under-testing includes one or more second source/drain regions and a gate structure arranged between the one or more first source/drain regions and the one or more second source/drain regions, and the second metallization level including a second test pad and one or more third interconnect lines connecting the one or more first interconnect lines with the second test pad.

Assignees

• Globalfoundries Inc

Inventors

• Yang Mankyu
• Vakada Vara Govindeswara Reddy
• Maciejewski Edward
• Greene Brian
• Ogino Atsushi
• Chauhan Vikrant
• Sengupta Prianka

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10D84/0158 Primary

  the components including FinFETs · CPC title