Integrated circuit package with embedded passive structures

Patent metadata

Field	Value
Publication number	US-9673173-B1
Application number	US-201514808743-A
Country	US
Kind code	B1
Filing date	Jul 24, 2015
Priority date	Jul 24, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

An integrated circuit package with embedded passive structures may include first and second integrated circuit dies that are surrounded by capacitor structures. A molding compound is deposited to encapsulate the integrated circuit dies and the capacitor structures. The molding compound is then attached to a redistribution wafer, in which the integrated circuit dies and the capacitor structures are electrically connected to metal routing layers of the redistribution wafer. A conductive layer is subsequently formed over the first integrated circuit die in the molding compound. The conductive layer is made up of additional metal routing layers and inductor structures. The integrated circuit package may further include a group of conductive vias that is formed in the molding compound. Each conductive via has a first end contacting the metal routing layers of the distribution wafer, and a second end contacting the conductive layer.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit package, comprising:
encapsulating first and second integrated circuit dies with a molding compound;
forming a passive component over the molding compound;
encapsulating the passive component in additional molding compound, wherein the additional molding compound directly contacts the molding compound; and
mounting the encapsulated first and second integrated circuit dies on a redistribution wafer, wherein the first integrated circuit die is interposed between the passive component and the redistribution wafer.

2. The method defined in claim 1 , further comprising:
forming a plurality of capacitor structures surrounding the first and second integrated circuit dies.

3. The method defined in claim 2 , wherein mounting the encapsulated first and second integrated circuit dies comprising:
attaching the encapsulated first and second integrated circuit dies to metal routing layers, wherein the metal routing layers are part of the redistribution wafer, and wherein the metal routing layers are electrically coupled to the first and second integrated circuit dies and the plurality of capacitor structures.

4. The method defined in claim 3 , further comprising:
forming a plurality of vias in the molding compound, wherein each of the plurality of vias comprises a first end contacting the metal routing layers and a second end contacting the passive component.

5. The method defined in claim 4 , wherein the second integrated circuit die is smaller than the first integrated circuit die, and wherein forming the passive component over the molding compound comprises:
forming conductive loops above the first integrated circuit die.

6. The method defined in claim 3 , further comprising:
forming a plurality of contact pads on top surfaces of the metal routing layers, wherein a first portion of the plurality of contact pads is electrically connected to the first integrated circuit die, and a second portion of the plurality of contact pads is electrically connected to the second integrated circuit die.

7. The method defined in claim 6 , further comprising:
forming a plurality of interconnects on bottom surfaces of the metal routing layers.

8. The method defined in claim 1 ,
wherein the molding compound and the additional molding compound are formed from the same material.

9. An integrated circuit package produced by a process comprising the steps of:
forming a non-conductive layer that encapsulates first and second integrated circuit dies;
forming a plurality of conductive vias through the non-conductive layer; and
forming a conductive layer over the non-conductive layer, wherein the conductive layer comprises a plurality of passive structures, each of which is connected to an end of each of the plurality of conductive vias.

10. The integrated circuit package defined in claim 9 , wherein the non-conductive layer comprises a molding layer.

11. The integrated circuit package defined in claim 9 , wherein the process of producing the integrated circuit package further comprises:
attaching the non-conductive layer to routing layers of a redistribution wafer.

12. The integrated circuit package defined in claim 9 , wherein the routing layer comprises a plurality of metal traces each of which is connected to another end of each of the plurality of conductive vias.

13. The integrated circuit package defined in claim 9 , wherein the process of producing the integrated circuit package further comprises:
forming an array of solder balls on a bottom surface of the routing layer.

14. The integrated circuit package defined in claim 9 , wherein the first and second integrated circuit dies are surrounded by a plurality of capacitor structures.

15. An integrated circuit package, comprising:
a first integrated circuit die;
a second integrated circuit die;
a conductive structure formed over the first integrated circuit die;
a molding compound layer that encapsulates the conductive structure, the first integrated circuit die, and the second integrated circuit die;
routing layers attached to a bottom surface of the molding compound layer; and
a plurality of vias formed in the molding compound layer, wherein each of the plurality of vias comprises a first end contacting the routing layers and a second end contacting the conductive structure.

16. The integrated circuit package defined in claim 15 , wherein the conductive structure further comprises a plurality of inductor elements, each of which is positioned above the first integrated circuit die.

17. The integrated circuit package defined in claim 16 , wherein each of the inductor elements comprises a conductive loop.

18. The integrated circuit package defined in claim 15 , wherein the routing layers are part of a redistribution wafer.

19. The integrated circuit package defined in claim 18 , the routing layers comprise redistribution layer structures that are electrically coupled to the first and second integrated circuit dies.

20. The integrated circuit package defined in claim 19 , further comprising:
a plurality of capacitor structures surrounding the first and second integrated circuit dies, wherein the plurality of capacitor structures is electrically coupled to the redistribution layer structures.

Assignees

• Altera Corp

Inventors

• Li Zhe
• Xie Yuanlin

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title