Semiconductor device, manufacturing method thereof, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9812490-B2
Application number	US-201414248948-A
Country	US
Kind code	B2
Filing date	Apr 9, 2014
Priority date	Dec 25, 2009
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other.

First claim

What is claimed is:

1. A semiconductor device configured as a backside illuminated solid-state imaging device, comprising:
a stacked semiconductor device which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit, and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit, and in which the pixel array is formed in a first semiconductor substrate included as part of the first semiconductor chip unit,
wherein a laminated insulating layer is disposed on the first semiconductor substrate,
wherein the first semiconductor chip unit has a connection hole and a through connection hole which both are formed in the first semiconductor substrate and a concave portion which is formed in the laminated insulating layer,
wherein a first set of connection wirings is formed so as to be buried in the connection hole, the through connection hole and the concave portion and electrically connects the first and second semiconductor chip units to each other,
wherein the first set of connection wirings is a unitary structure,
wherein a surface of at least a part of the first set of connection wirings is higher than a surface of the laminated insulating layer in a first section, and
wherein the surface of the part of the first set of connection wirings is lower than the surface of the laminated insulating layer in a second section.

2. The semiconductor device according to claim 1 ,
wherein the first set of connection wirings includes a first connection conductor, a second connection conductor, and a connecting connection conductor,
wherein the first connection conductor is connected to a first connection pad connected to a wiring inside the multi-layer wiring layer in the first semiconductor chip unit, and
wherein the second connection conductor is a through connection conductor perforated through the first semiconductor chip unit and is connected to a second connection pad connected to a wiring inside the multi-layer wiring layer in the second semiconductor chip unit.

3. The semiconductor device according to claim 2 , further comprising:
a connection pad array in which pairs of first and second connection pads are arranged in a vertical direction and a horizontal direction and the pairs of first and second connection pads are arranged in a plurality of stages in the vertical direction,
wherein wirings respectively corresponding to vertical signal lines are connected to the pairs of first and second connection pads arranged in the plurality of stages.

4. The semiconductor device according to claim 3 , wherein in the first semiconductor chip unit, the first connection pad is formed of a first layer metal of the multi-layer wiring layer and the wiring connected to the first connection pad is formed of a layer metal subsequent to a second layer metal.

5. The semiconductor device according to claim 4 , wherein a shield wiring is formed by a layer metal between the first connection pad and the wiring.

6. The semiconductor device according to claim 3 , further comprising:
a connection pad array in which pairs of first and second connection pads are arranged in the vertical direction and a horizontal direction and the pairs of first and second connection pads are arranged in a plurality of stages in the vertical direction,
wherein wirings respectively corresponding to vertical signal lines are connected to the pairs of first and second connection pads arranged in the plurality of stages.

7. A method of manufacturing a semiconductor device configured as a backside illuminated solid-state imaging device, comprising:
bonding two or more semiconductor wafers to each other, which at least include a first semiconductor wafer, in which a pixel array and a multi-layer wiring layer are formed in a region serving as a first semiconductor chip unit, and a second semiconductor wafer, in which a logic circuit and a multi-layer wiring layer are formed in a region serving as a second semiconductor chip unit;
forming a connection hole reaching a first connection pad connected to a wiring of the multi-layer wiring layer in the first semiconductor chip unit and a through connection hole perforated through the first semiconductor chip unit and reaching a second connection pad connected to a wiring of the multi-layer wiring layer in the second semiconductor chip unit; and
forming a plurality of connection wirings connecting the first and second semiconductor chip units,
wherein forming a plurality of connection wirings includes forming a connection conductor and a through connection conductor connected to the first and second connection pads in the connection hole and the through connection hole, respectively, and forming a connecting connection conductor that connects the connection conductor and the through connection conductor to each other,
wherein a laminated insulating layer is disposed on the first semiconductor wafer,
wherein a surface of at least a part of the connection conductor and the through connection conductor are farther from a surface of the second semiconductor wafer than a surface of the laminated insulating layer,
wherein the surface of the part of the connection conductor and the through connection conductor is higher than the surface of the laminated insulating layer in a first section,
wherein the surface of the part of the connection conductor and the through connection conductor is lower than the surface of the laminated insulating layer in a second section,
wherein the connecting connection conductor extends over all of an end of the connection conductor and over all of an end of the through connection conductor,
wherein the connecting connection conductor, the connection conductor and the through connection conductor are a unitary metal material, and
dividing the semiconductor wafers formed as a finished product into chips.

8. The method according to claim 7 ,
wherein the first connection pad is formed of a first layer metal of the multi-layer wiring layer, and
wherein the wiring connected to the first connection pad is formed of a layer metal subsequent to a second layer metal.

9. An electronic apparatus comprising:
a solid-state imaging device;
an optical system guiding incident light to a photoelectric conversion unit of the solid-state imaging device;
a signal processing circuit processing a signal output from the solid-state imaging device,
wherein the solid-state imaging device, which is configured as a backside illuminated solid-state imaging device, includes
a stacked semiconductor device which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit, and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit, and in which the pixel array is formed in a first semiconductor substrate included as part of the first semiconductor chip unit,

wherein a laminated insulating layer is disposed on the first semiconductor chip unit,
wherein the first semiconductor chip unit has a connection hole and a through connection hole which both are formed in the first semiconductor substrate and a concave portion which is formed in the laminated insulating layer,
wherein a first set of connection wirings is formed so as to be buried in the connection hole, the through connection hole and the concave portion and electrically connects the first and second semiconductor chip units to each other,
wherein the first set of connection wirings is a unitary structure,
wherein a surface of at least a par

Assignees

• Sony Corp

Inventors

• Itonaga Kazuichiroh
• Horiike Machiko

Classifications

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title