Clock tree routing in a chip stack

Patent metadata

Field	Value
Publication number	US-2024103562-A1
Application number	US-202318521301-A
Country	US
Kind code	A1
Filing date	Nov 28, 2023
Priority date	Dec 18, 2020
Publication date	Mar 28, 2024
Grant date	—

Abstract

Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

First claim

What is claimed is:

1 . An integrated circuit (IC) device comprising:
a chip stack comprising a plurality of IC chips, the plurality of IC chips comprising:
a first IC chip comprising first leaf nodes;
a second IC chip comprising second leaf nodes; and
a first clock tree comprising first in-chip routing within the first IC chip and coupled to the first leaf nodes, wherein a first out-of-chip leaf-level connection bridge couples one of the first leaf nodes with one of the se…

Assignees

• Xilinx Inc

Inventors

• Gaide Brian C

Classifications

• H10W90/792

  Electricity · mapped topic

• H10W72/90

  Electricity · mapped topic

• H10W90/26

  Electricity · mapped topic

• H10W90/297

  Electricity · mapped topic

• H10W90/20

  Electricity · mapped topic