Buffer layer(s) on a stacked structure having a via

Patent metadata

Field	Value
Publication number	US-9793243-B2
Application number	US-201414459144-A
Country	US
Kind code	B2
Filing date	Aug 13, 2014
Priority date	Aug 13, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

First claim

What is claimed is:

1. A method comprising:
bonding a first substrate to a second substrate, the second substrate comprising a semiconductor substrate and active devices on the semiconductor substrate;
forming a via from a side of the semiconductor substrate and at least extending through the semiconductor substrate, wherein the side of the semiconductor substrate is opposite the active devices;
forming a first stress buffer layer on the side of the semiconductor substrate opposite the active devices;
forming a post-passivation interconnect (PPI) structure on the first stress buffer layer and electrically coupled to the via, wherein the forming the PPI structure includes forming the PPI structure with openings through the PPI structure; and
forming a second stress buffer layer on the PPI structure and the first stress buffer layer, wherein forming the second stress buffer layer fills the openings in the PPI structure with portions of the second stress buffer layer.

2. The method of claim 1 , wherein the bonding consists essentially of dielectric-to-dielectric bonding.

3. The method of claim 1 , wherein the bonding includes bonding a first metallization pattern of the first substrate to a second metallization pattern of the second substrate.

4. The method of claim 1 , wherein the forming the via includes forming the via extending into the first substrate.

5. The method of claim 1 further comprising forming a contact bump electrically coupled to the PPI structure.

6. A method comprising:
bonding a first substrate to a second substrate, the first substrate comprising a semiconductor substrate, active devices on the semiconductor substrate, and an interconnect structure, the interconnect structure and active devices being on a first side of the semiconductor substrate, the interconnect structure being disposed between the semiconductor substrate and the second substrate after the bonding;
forming a conductive pad on a second side of the semiconductor substrate opposite from the first side of the semiconductor substrate, the conductive pad being electrically coupled to the interconnect structure;
forming a passivation layer on the conductive pad and on the second side of the semiconductor substrate;
forming a first stress buffer layer on the passivation layer;
forming an interconnect structure on the first stress buffer layer and through an opening through the first stress buffer layer and the passivation layer to the conductive pad;
forming a second stress buffer layer on the interconnect structure and the first stress buffer layer, the second stress buffer layer contacting the interconnect structure and the first stress buffer layer, first openings being through the interconnect structure in a region of the interconnect structure, portions of the second stress buffer layer are disposed in the first openings; and
forming an external electrical connector contacting the region of the interconnect structure.

7. The method of claim 6 further comprising forming a through via extending from the second side of the semiconductor substrate through the semiconductor substrate at least to the interconnect structure, the conductive pad being electrically coupled to the through via.

8. The method of claim 6 , wherein the through via further extends into the second substrate.

9. The method of claim 6 wherein forming the external electrical connector further comprises forming the external electrical connector on the second stress buffer layer, through a second opening through the second stress buffer layer, and contacting the interconnect structure.

10. The method of claim 6 , wherein each of the first stress buffer layer and the second stress buffer layer has a Young's modulus in a range from 2 GPa to 4 GPa, and a tensile strength in a range from 90 MPa to 200 MPa.

11. The method of claim 6 , wherein the bonding consists essentially of dielectric-to-dielectric bonding.

12. The method of claim 6 , wherein the bonding includes bonding a first metallization pattern of the first substrate to a second metallization pattern of the second substrate.

13. The method of claim 6 , wherein forming the external electrical connection structure comprises:
forming an under-bump structure contacting the interconnect structure and on a surface of the second stress buffer layer distal from the first stress buffer layer, the under-bump structure being through an opening of the second stress buffer layer; and
forming a bump contact on the under-bump structure.

14. A method comprising:
bonding a first substrate to a second substrate, the first substrate comprising a first semiconductor substrate, active devices on the first semiconductor substrate, and a first interconnect structure on the first semiconductor substrate, the second substrate comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate, wherein after the bonding, the first interconnect structure and the second interconnect structure are disposed between the first semiconductor substrate and the second semiconductor substrate;
forming a through via extending from a side of the first semiconductor substrate opposite from the first interconnect structure through the first semiconductor substrate at least to the first interconnect structure;
forming a pad on the side of the first semiconductor substrate opposite from the first interconnect structure and the active devices, the pad being electrically coupled to the through via;
forming a passivation layer on the pad and the first semiconductor substrate opposite from the first interconnect structure and the active devices;
forming a first stress buffer layer on the passivation layer, the passivation layer being disposed between the first stress buffer layer and the first semiconductor substrate;
forming a post-passivation interconnect (PPI) structure on the first stress buffer layer, the PPI structure extending through an opening through the first stress buffer layer and the passivation layer to be electrically coupled to the pad;
forming a second stress buffer layer on the PPI structure and the first stress buffer layer, the PPI structure being disposed at least in part between the first stress buffer layer and the second stress buffer layer, the second stress buffer layer contacting the PPI structure and the first stress buffer layer; and
forming an external electrical connection structure through an opening of the second stress buffer layer and contacting the PPI structure, the PPI structure having PPI openings in a region where the external electrical connection structure contacts the PPI structure, the second stress buffer layer being at least partially disposed in the PPI openings.

15. The method of claim 14 , wherein the through via extends into the second interconnect structure.

16. The method of claim 14 , wherein the through via extends to the first interconnect structure.

17. The method of claim 14 , wherein a first dielectric layer of the first substrate is bonded to a second dielectric layer of the second substrate at a bonding interface during the bonding, wherein the bonding interface consists essentially of dielectric-to-dielectric bonding during the bonding.

18. The method of claim 14 , wherein the external electrical connection structure comprises:
an under-bump structure contacting the PPI structure and on a surface of the second stress buffer layer distal from the first stress buffer layer, the under-bump structure being through the opening of the second stress buffer layer; and
a bump c

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Chen-Fa
• Tsai Cheng-Yuan
• Tu Yeur-Luen
• Tsai Chia-Shiung

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title