Bumpless build-up layer package with pre-stacked microelectronic devices

Patent metadata

Field	Value
Publication number	US-9831213-B2
Application number	US-201615170833-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Aug 26, 2010
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

First claim

What is claimed is:

1. A microelectronic package, comprising:
a bumpless build-up layer (BBUL) substrate;
a plurality of stacked microelectronic dies above the BBUL substrate, the plurality of stacked microelectronic dies having a bottommost microelectronic die proximate the BBUL substrate, and a next bottommost microelectronic die above the bottommost microelectronic die, wherein the bottommost microelectronic die has a plurality of front side lands on an active portion facing the BBUL substrate and a plurality of backside lands facing the next bottommost microelectronic die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost microelectronic die, wherein the next bottommost microelectronic die has a plurality of front side lands facing the bottommost microelectronic die, wherein the plurality of backside lands of the bottommost microelectronic die is directly coupled to the plurality of front side lands of the next bottommost microelectronic die by a solder layer, and wherein the plurality of front side lands of the bottommost microelectronic die electrically couples the bottommost microelectronic die to the BBUL substrate, wherein the TSVs of the bottommost microelectronic die are in direct contact with the backside lands of the bottommost microelectronic die but are not in direct contact with the front side lands of the bottommost microelectronic die;
an underfill material layer between the bottommost microelectronic die and the next bottommost microelectronic die; and
an encapsulation material over the BBUL substrate and laterally adjacent to the bottommost microelectronic die, the next bottommost microelectronic die and the underfill material layer, wherein the encapsulation material is separate and distinct from the underfill material layer.

2. The microelectronic package of claim 1 , wherein the encapsulation material has an uppermost surface substantially co-planar with an uppermost surface of an uppermost microelectronic die of the plurality of stacked microelectronic dies.

3. The microelectronic package of claim 2 , wherein the next bottommost microelectronic die is the uppermost microelectronic die of the plurality of stacked microelectronic dies, and wherein the uppermost surface of the encapsulation material is substantially co-planar with an uppermost surface of the next bottommost microelectronic die distal from the BBUL substrate.

4. The microelectronic package of claim 1 , wherein the encapsulation material comprises a silica-filled epoxy.

5. A method of fabricating a microelectronic package, the method comprising:
forming a plurality of stacked dies comprising at least a first die and a second die above a carrier, wherein the first die has a plurality of front side lands and has a plurality of backside lands facing the second die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the first die, wherein the second die has a plurality of front side lands facing the first die, wherein the plurality of backside lands of the first die is directly coupled to the plurality of front side lands of the second die by a solder layer;
subsequent to forming the plurality of stacked dies, forming an underfill material layer between the first die and the second die;
subsequent to forming the underfill material layer, forming an encapsulation material over the carrier and laterally adjacent to the first die, the second die and the underfill material layer;
subsequent to forming the encapsulation material, forming a bumpless build-up layer (BBUL) substrate over the encapsulation material, wherein the plurality of front side lands of the first die electrically couples the first die to the BBUL substrate; and
subsequent to forming the BBUL substrate, removing the carrier.

6. The method of claim 5 , wherein forming the encapsulation material comprises forming a silica-filled epoxy.

7. The method of claim 5 , wherein the encapsulation material has a lowermost surface substantially co-planar with a lowermost surface of a lowermost die of the plurality of stacked dies.

8. The method of claim 7 , wherein the second die is the lowermost die of the plurality of stacked dies, and wherein the lowermost surface of the encapsulation material is substantially co-planar with lowermost surface of the second die proximate the carrier.

9. The method of claim 5 , wherein the TSVs of the first die are in direct contact with the backside lands of the bottommost die but are not in direct contact with the front side lands of the bottommost die.

10. A microelectronic package, comprising:
a bumpless build-up layer (BBUL) substrate;
a plurality of stacked dies above the BBUL substrate, the plurality of stacked dies having a bottommost die proximate the BBUL substrate, and a next bottommost die above the bottommost die, wherein the bottommost die has a plurality of front side lands facing the BBUL substrate and a plurality of backside lands facing the next bottommost die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost die, wherein the next bottommost die has a plurality of front side lands facing the bottommost die, wherein the plurality of backside lands of the bottommost die is directly coupled to the plurality of front side lands of the next bottommost die by a solder layer, and wherein the plurality of front side lands of the bottommost die electrically couples the bottommost die to the BBUL substrate, wherein the TSVs of the bottommost die are in direct contact with the backside lands of the bottommost die but are not in direct contact with the front side lands of the bottommost die;
an underfill material layer between the bottommost die and the next bottommost die; and
an encapsulation material over the BBUL substrate and laterally adjacent to the bottommost die, the next bottommost die and the underfill material layer, wherein the encapsulation material is separate and distinct from the underfill material layer.

Assignees

• Intel Corp

Inventors

• Malatkar Pramod

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title