Stress compensation for wafer to wafer bonding
US-2020303191-A1 · Sep 24, 2020 · US
using blanket deposition
using blanket deposition · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W72/01331 |
| Official title | {using blanket deposition} |
| Display label | using blanket deposition |
| Total patents | 80 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 15 |
| 2016 | 17 |
| 2017 | 7 |
| 2018 | 9 |
| 2019 | 8 |
| 2020 | 8 |
| 2021 | 4 |
| 2022 | 4 |
| 2023 | 2 |
| 2024 | 2 |
| 2025 | 3 |
| 2026 | 1 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Packaged semiconductor components having substantially rigid support members
US-10763185-B2 · Sep 1, 2020 · US
Methods and systems for manufacturing semiconductor devices
US-2020212001-A1 · Jul 2, 2020 · US
Contact structures with porous networks for solder connections, and methods of fabricating same
US-10531574-B2 · Jan 7, 2020 · US
Thermal management solutions for stacked integrated circuit devices using jumping drops vapor chambers
US-2019393192-A1 · Dec 26, 2019 · US
Thermal management solutions for stacked integrated circuit devices using jumping drops vapor chambers
US-2019393193-A1 · Dec 26, 2019 · US
Semiconductor Devices Including a Metal Silicide Layer and Methods for Manufacturing Thereof
US-2019355691-A1 · Nov 21, 2019 · US
Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same
US-2019273037-A1 · Sep 5, 2019 · US
Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
US-2019252281-A1 · Aug 15, 2019 · US
Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
US-10312173-B2 · Jun 4, 2019 · US
Method of manufacturing stacked mounting structure
US-10244639-B2 · Mar 26, 2019 · US
High-conductivity bonding of metal nanowire arrays
US-10180288-B2 · Jan 15, 2019 · US
Ultrathin Layer for Forming a Capacitive Interface Between Joined Integrated Circuit Component
US-2018366446-A1 · Dec 20, 2018 · US
Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
US-2018358324-A1 · Dec 13, 2018 · US
Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
US-10083931-B2 · Sep 25, 2018 · US
Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
US-2018211896-A1 · Jul 26, 2018 · US
Ultrathin layer for forming a capacitive interface between joined integrated circuit components
US-10032751-B2 · Jul 24, 2018 · US
Contact structures with porous networks for solder connections, and methods of fabricating same
US-2018124927-A1 · May 3, 2018 · US
Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
US-9960094-B2 · May 1, 2018 · US
Contact structures with porous networks for solder connections, and methods of fabricating same
US-9888584-B2 · Feb 6, 2018 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W72/01331?
- CPC H10W72/01331 is the Cooperative Patent Classification code for “using blanket deposition.”
- How many patents are filed under CPC H10W72/01331 (using blanket deposition)?
- Our database includes 80 publications tagged with this CPC code.
- Is patent activity under CPC H10W72/01331 growing?
- Publication counts under this code: 2 in 2024 vs 3 in 2025 (latest complete years).