Packaged semiconductor components having substantially rigid support members

Patent metadata

Field	Value
Publication number	US-10763185-B2
Application number	US-201916391732-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Mar 13, 2007
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

First claim

We claim:

1. A packaged semiconductor component, comprising:
a first semiconductor die having a first composition, a first surface, a first bond pad located on or near the first surface, and a second surface opposite the first surface;
a second semiconductor die having a same size as the first semiconductor die;
a support member between the first semiconductor die and the second semiconductor die, the support member attached to the first surface of the first semiconductor die, the support member being at least substantially rigid and having a second composition different from the first composition of the first semiconductor die, the support member having a size less than a size of the first semiconductor die whereby the first bond pad located on or near the first surface is not covered by the support member;
a substrate carrying the first semiconductor die, the support member and the second semiconductor die; and
an encapsulant at least partially encasing the first semiconductor die, the support member, the second semiconductor die, and the substrate,
wherein the first and second semiconductor dies include a plurality of second bond pads at or near a surface of the first and second semiconductor dies,
wherein the plurality of second bond pads of each of the first and second semiconductor dies are vertically aligned, and
wherein the support member comprises a plurality of heat conducting fins sandwiched between two plates.

2. The packaged semiconductor component of claim 1 wherein the support member has a thickness sufficient to enable the plurality of the bond pads of the first and second semiconductor dies to be wirebonded to connection sites at the substrate.

3. The packaged semiconductor component of claim 1 wherein a thickness of the support member is about 100 microns to about 3 mm.

4. The packaged semiconductor component of claim 1 wherein the support member comprises a metal or a metal alloy.

5. The packaged semiconductor component of claim 1 further comprising a first adhesive attaching the support member to the first die, and a second adhesive attaching the second die to the substrate.

6. The packaged semiconductor component of claim 5 further comprising a third adhesive attaching the support member to the second die.

7. A packaged semiconductor component, comprising:
a first semiconductor die having a first surface, a first bond pad located on or near the first surface, and a second surface opposite the first surface;
a second semiconductor die having a same size as the first semiconductor die;
a support member between the first semiconductor die and the second semiconductor die, the support member attached to the first surface of the first semiconductor die, the support member including a plate constructed from a metal and/or a metal alloy, the support member having a size less than a size of the first semiconductor die whereby the first bond pad located on or near the first surface is not covered by the support member;
a substrate carrying the first semiconductor die, the support member, and the second semiconductor die; and
an encapsulant at least partially encasing the semiconductor dies, the support member, and the substrate,
wherein the first and second semiconductor dies include a plurality of second bond pads at or near a surface of the first and second semiconductor dies, and
wherein the support member comprises a plurality of heat conducting fins sandwiched between two plates.

8. The packaged semiconductor component of claim 7 wherein the support member has a thickness sufficient to enable the bond pads of the first and second semiconductor dies to wirebond to connection sites at the substrate.

9. The packaged semiconductor component of claim 7 wherein a thickness of the support member is about 100 microns to about 3 mm.

10. The packaged semiconductor component of claim 7 further comprising a first adhesive attaching the support member to the first die, and a second adhesive attaching the second die to the substrate.

11. The packaged semiconductor component of claim 10 further comprising a third adhesive attaching the support member to the second die.

Assignees

• Micron Technology Inc

Inventors

• Schwab Matt E
• Brooks J Michael
• Corisis David J

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title