Ultrathin layer for forming a capacitive interface between joined integrated circuit components

Patent metadata

Field	Value
Publication number	US-10032751-B2
Application number	US-201615247705-A
Country	US
Kind code	B2
Filing date	Aug 25, 2016
Priority date	Sep 28, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

First claim

The invention claimed is:

1. A method of coupling microelectronic components, comprising:
selecting a first integrated circuit die, the first integrated circuit die including a first surface comprising at least one conductive area with a first surface area;
selecting a second integrated circuit die, the second integrated circuit die including a second surface comprising at least one conductive area with a second surface area;
forming a first ultrathin layer comprising a first dielectric on the first surface of the first integrated circuit die, the first ultrathin layer comprising a first thickness;
forming a second ultrathin layer comprising a second dielectric on the second surface of the second integrated circuit die, the second ultrathin layer comprising a second thickness;
forming a third ultrathin layer comprising a polymer between the first ultrathin layer comprising the first dielectric and the second ultrathin layer comprising the second dielectric, the third ultrathin layer comprising a third thickness;
coupling the first integrated circuit die and the second integrated circuit die in a stack to form a capacitive interface between the at least one conductive area of the first integrated circuit die having a first surface area and the at least one conductive area of the second integrated circuit die having a second surface area; and
wherein the combined thickness of the first thickness of the first dielectric, the second thickness of the second dielectric, and the third thickness of the polymer is less than 25 nanometers.

2. The method of claim 1 , wherein the first thickness, the second thickness, and the third thickness are all different thicknesses.

3. The method of claim 1 , wherein the first thickness, the second thickness, and the third thickness are each less than 2 nanometers apiece.

4. The method of claim 1 , wherein the first dielectric and the second dielectric each comprise silicon dioxide.

5. The method of claim 1 , wherein at least one of the first dielectric and the second dielectric is selected from the group consisting of silicon monoxide, silicon trioxide, aluminum oxide, hafnium oxide, a high-κ ionic metal oxide, a hybrid oxygen-plasma-grown metal oxide & alkylphosphonic acid self-assembled monolayer (SAM), a polymer film, and an ionic metal oxide membrane.

6. The method of claim 1 , wherein at least one of the first dielectric and the second dielectric comprises an atomic layer of hafnium oxide with a thickness of 1-2 nanometers.

7. The method of claim 1 , wherein at least one of the first dielectric and the second dielectric comprises a layer of the metal oxide & alkylphosphonic acid self-assembled monolayer (SAM) having a thickness of approximately 5-6 nanometers and a capacitance per unit area of approximately 500-800 nF/cm2.

8. The method of claim 1 , further comprising:
applying a coating of an etch stop or a lapping-polishing stop to at least the first surface or the second surface;
forming the first ultrathin layer of the first dielectric or the second ultrathin layer of the second dielectric on the coating of the etch stop or the coating of the lapping-polishing stop; and
etching or lapping the ultrathin layer of the first dielectric or the second dielectric, wherein the etch stop or the lapping stop precisely controls a thickness of the first dielectric or the second dielectric and protects underlying structures from the etching or lapping.

9. The method of claim 8 , wherein the etch stop is selected from the group consisting of a silicon dioxide etch stop, a boron etch stop, an aluminum oxide etch stop, a polysilicon etch stop, a titanium oxide etch stop, and a silicon nitride etch stop.

10. The method of claim 1 , wherein the first ultrathin layer of the first dielectric or the second ultrathin layer of the second dielectric comprises a layer capable of adhering the integrated circuit dies to each other.

11. The method of claim 1 , further comprising mechanically securing the first integrated circuit die and the second integrated circuit die together at an edge of the stack.

12. The method of claim 1 , further comprising locating electrical power and electrical grounding connections between the integrated circuit dies at an edge of the stack.

13. The method of claim 1 , further comprising adjusting a capacitance of the capacitive interface by selecting a thickness of the third ultrathin layer comprising the polymer between the first ultrathin layer and the second ultrathin layer.

14. The method of claim 1 , further comprising adjusting a capacitance of the capacitive interface by staggering an alignment of the at least one conductive area of the first integrated circuit die having a first surface area and the at least one conductive area of the second integrated circuit die having a second surface area.

15. The method of claim 1 , further comprising adjusting a capacitance of the capacitive interface by selecting a thickness of the third ultrathin layer comprising the polymer between the first ultrathin layer and the second ultrathin layer, and staggering an alignment of the at least one conductive area of the first integrated circuit die having a first surface area and the at least one conductive area of the second integrated circuit die having a second surface area.

Assignees

• Invensas Corp

Inventors

• Haba Belgacem
• Sitaram Arkalgud R

Classifications

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01931

  using blanket deposition · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title