Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components

Patent metadata

Field	Value
Publication number	US-10312173-B2
Application number	US-201815936715-A
Country	US
Kind code	B2
Filing date	Mar 27, 2018
Priority date	Mar 13, 2007
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

First claim

We claim:

1. A packaged semiconductor component, comprising:
a semiconductor die having a first composition, a first surface, a bond pad located on or near the first surface, and a second surface opposite the first surface;
an array of photo sensors at least partially embedded in the semiconductor die proximate to the first surface;
a support member attached to the first surface of the semiconductor die, the support member being at least substantially rigid and having a second composition different from the first composition of the semiconductor die, the support member including an opening generally aligned with the bond pad located on or near the first surface;
a substrate carrying the semiconductor die and the support member attached to the semiconductor die; and
an encapsulant at least partially encasing the semiconductor die, the support member, and the substrate.

2. The packaged semiconductor component of claim 1 wherein the support member includes at least one of following: a slot, a channel, or an aperture.

3. The packaged semiconductor component of claim 1 wherein a thickness of the support member is about 100 microns to about 3 mm.

4. The packaged semiconductor component of claim 1 wherein the support member comprises a laminated structure having a plurality of different materials, wherein at least one of the different materials is substantially rigid.

5. The packaged semiconductor component of claim 1 , further comprising a glass member at the array of photo sensors.

6. A packaged semiconductor component, comprising:
a semiconductor die having a first surface, a bond pad located on or near the first surface, and a second surface opposite the first surface;
a photo sensor at least partially embedded in the semiconductor die proximate to the first surface;
a support member attached to the first surface of semiconductor die, the support member including a plate constructed from a metal and/or a metal alloy and having a composition different from a composition of the semiconductor die, the support member including an opening generally aligned with the bond pad located on or near the first surface;
a substrate carrying the semiconductor die and the attached support member; and
an encapsulant at least partially encasing the semiconductor dies, the support member, and the substrate.

7. The packaged semiconductor component of claim 6 wherein the support member includes at least one of following: a slot, a channel, or an aperture.

8. The packaged semiconductor component of claim 6 wherein a thickness of the support member is about 00 microns to about 3 mm.

9. The packaged semiconductor component of claim 6 wherein the support member comprises a laminated structure having a plurality of different materials, wherein at least one of the different materials is substantially rigid.

10. The packaged semiconductor component of claim 6 further comprising a glass member generally flush with the photo sensor at the first surface.

Assignees

• Micron Technology Inc

Inventors

• Schwab Matt E
• Brooks J Michael
• Corisis David J

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title