Semiconductor structure with integrated passive structures
US-2017338145-A1 · Nov 23, 2017 · US
the processing being a planarisation of insulating layers
the processing being a planarisation of insulating layers · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10P70/237 |
| Official title | {the processing being a planarisation of insulating layers} |
| Display label | the processing being a planarisation of insulating layers |
| Total patents | 312 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 14 |
| 2016 | 24 |
| 2017 | 27 |
| 2018 | 30 |
| 2019 | 31 |
| 2020 | 29 |
| 2021 | 41 |
| 2022 | 34 |
| 2023 | 31 |
| 2024 | 20 |
| 2025 | 26 |
| 2026 | 5 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Cleaning apparatus, chemical mechanical polishing system including the same, cleaning method after chemical mechanical polishing, and method of manufacturing semiconductor device including the same
US-2017301553-A1 · Oct 19, 2017 · US
Method of bonding semiconductor substrates
US-2017301646-A1 · Oct 19, 2017 · US
Engineered etched interfaces for high performance junctions
US-2017287717-A1 · Oct 5, 2017 · US
Semiconductor structure with integrated passive structures
US-9768195-B2 · Sep 19, 2017 · US
Cleaning liquid and method for cleaning
US-2017253840-A1 · Sep 7, 2017 · US
Method of fabricating semiconductor structure using planarization process and cleaning process
US-9748111-B2 · Aug 29, 2017 · US
Semiconductor structure with integrated passive structures
US-2017236898-A1 · Aug 17, 2017 · US
Method of fabricating semiconductor device
US-9728446-B2 · Aug 8, 2017 · US
Method of fabricating semiconductor structure using planarization process and cleaning process
US-2017221723-A1 · Aug 3, 2017 · US
Mechanisms for forming oxide layer over exposed polysilicon during a chemical mechanical polishing (CMP) process
US-9711374-B2 · Jul 18, 2017 · US
Semiconductor device having epitaxial layer with planar surface and protrusions
US-2017200824-A1 · Jul 13, 2017 · US
Detecting the Cleanness of Wafer After Post-CMP Cleaning
US-2017194217-A1 · Jul 6, 2017 · US
Semiconductor structure with integrated passive structures
US-9698159-B2 · Jul 4, 2017 · US
Post-polish wafer cleaning
US-2017178918-A1 · Jun 22, 2017 · US
Methods and solutions for cleaning ingaas (or iii-v) substrates
US-2017162379-A1 · Jun 8, 2017 · US
Manufacturing method of semiconductor device, and semiconductor device
US-9673073-B2 · Jun 6, 2017 · US
Semiconductor structure with integrated passive structures
US-9659961-B2 · May 23, 2017 · US
Method of removing a hard mask layer on a gate structure while forming a protective layer on the surface of a substrate
US-9646889-B1 · May 9, 2017 · US
Method and system for cleansing wafer in CMP process of semiconductor manufacturing fabrication
US-9610615-B2 · Apr 4, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10P70/237?
- CPC H10P70/237 is the Cooperative Patent Classification code for “the processing being a planarisation of insulating layers.”
- How many patents are filed under CPC H10P70/237 (the processing being a planarisation of insulating layers)?
- Our database includes 312 publications tagged with this CPC code.
- Is patent activity under CPC H10P70/237 growing?
- Publication counts under this code: 20 in 2024 vs 26 in 2025 (latest complete years).