Method of fabricating semiconductor structure using planarization process and cleaning process

Patent metadata

Field	Value
Publication number	US-9748111-B2
Application number	US-201615012821-A
Country	US
Kind code	B2
Filing date	Feb 1, 2016
Priority date	Feb 1, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, comprising the steps of:
providing a substrate;
forming a first layer on the substrate;
conformally forming a second layer over the first layer, wherein the second layer and the first layer have different compositions;
forming a third layer over the second layer, wherein the third layer and the second layer have different compositions;
performing a planarizing process on the third layer until portions of the second layer are exposed so as to produce a remaining third layer and an exposed second layer;
performing a first cleaning process comprising a step of providing hydrofluoric acid to the remaining third layer and the exposed second layer and a step of providing an aqueous oxidant to the remaining third layer and the exposed second layer, wherein an amount of the remaining third layer removed in the first cleaning process is greater than the exposed second layer removed in the first cleaning process, wherein a top surface of the third layer is lower than a top surface of the second layer when the first cleaning process is completed;
performing a second cleaning process to removing the exposed second layer by phosphoric acid until portions of the first layer are exposed after the first cleaning process; and
etching back the second layer and the first layer.

2. The method of claim 1 , wherein the first layer is a multilayer comprising at least a silicon layer.

3. The method of claim 1 , wherein the first layer is made of polysilicon or amorphous silicon.

4. The method of claim 1 , wherein the second layer is made of silicon nitride, silicon oxynitride (SiON), SiCN, SiOCN or a combination thereof.

5. The method of claim 1 , wherein the third layer is made of silicon oxide.

6. The method of claim 1 , wherein the step of providing the hydrofluoric acid is performed before the step of providing the aqueous oxidant, and the aqueous oxidant is an aqueous mixture of hydrogen peroxide (H 2 O2) and sulfuric acid (H 2 SO 4 ).

7. The method of claim 6 , after the step of providing the aqueous oxidant, further comprising:
providing further aqueous oxidant to the remaining third layer and the exposed second layer, wherein the further aqueous oxidant is an aqueous mixture of hydrogen peroxide (H 2 O 2 ) and ammonium hydroxide (NH 4 OH).

8. The method of claim 1 , wherein the step of removing the exposed second layer comprises providing phosphoric acid (H 3 PO 4 ) having a temperature of 150° C. to 180° C.

9. The method of claim 1 , wherein the step of providing the hydrofluoric acid and the step of providing the aqueous oxidant are performed concurrently.

10. The method of claim 9 , wherein the aqueous oxidant is an aqueous solution of ozone (O 3 ).

11. The method of claim 10 , wherein the hydrofluoric acid and the aqueous solution of ozone are distributed in deionized water.

12. The method of claim 1 , wherein the substrate comprises fin-shaped structures, gate structures or interconnection structures thereon.

13. A method for fabricating a semiconductor structure, comprising the steps of:
providing a substrate;
forming a first set of stripe-shaped structures and a second set of stripe-shaped structures on the substrate, wherein there is a space between the first and second sets of stripe-shaped structures;
forming a first layer over the first and second sets of stripe-shaped structures so as to form a recess on the surface of the first layer, wherein the recess is directly above the space between the first and second sets of stripe-shaped structures;
conformally forming a second layer over the first layer;
forming a third layer over the second layer;
performing a planarizing process on the third layer until portions of the second layer are exposed so as to produce a remaining third layer in the recess and an exposed second layer, wherein the third layer has an etch rate greater than an etch rate of the second layer in the planarizing process;
performing a first cleaning process comprising a step of providing hydrofluoric acid to the remaining third layer and the exposed second layer and a step of providing an aqueous oxidant to the remaining third layer and the exposed second layer, wherein an amount of the remaining third layer removed in the first cleaning process is greater than the exposed second layer removed in the first cleaning process, wherein a top surface of the third layer is lower than a top surface of the second layer when the first cleaning process is completed;
performing a second cleaning process to removing the exposed second layer by phosphoric acid until portions of the first layer are exposed after the first cleaning process; and
etching back the second layer and the first layer.

14. The method of claim 13 , wherein the first layer and the second layer have different compositions.

15. The method of claim 13 , wherein the second layer and the third layer have different compositions.

16. The method of claim 13 , wherein the space between the first and second sets of stripe-shaped structures has a first distance greater than spacing between two adjacent stripe-shaped structures.

17. The method of claim 13 , further comprising generating a plurality of organic particles on the third layer and the second layer during the step of performing a planarizing process on the third layer.

18. The method of claim 17 , wherein the particles are removed completely when the steps of providing the hydrofluoric acid and providing the aqueous oxidant are completed.

Assignees

• United Microelectronics Corp

Inventors

• Ye Yi-Liang
• Chen Kuang-Hsiu
• Liu Chueh-Yang
• Wang Yu-Ren

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P70/277

  the processing being a planarisation of conductive layers · CPC title

• H10P70/237

  the processing being a planarisation of insulating layers · CPC title