FORMING SELF-ALIGNED NiSi PLACEMENT WITH IMPROVED PERFORMANCE AND YIELD
US-2016163702-A1 · Jun 9, 2016 · US
Semiconductor device having epitaxial layer with planar surface and protrusions
US2017200824A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017200824-A1 |
| Application number | US-201715469569-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 26, 2017 |
| Priority date | Dec 25, 2015 |
| Publication date | Jul 13, 2017 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device, comprising: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, wherein the epitaxial layer comprises a planar surface and protrusions adjacent to two sides of the planar surface. 2 . The semiconductor device of claim 1 , further comprising a contact plug embedded in part of the epitaxial layer, wherein a bottom surface of the contact plug comprises an arc. 3 . The semiconductor device of claim 2 , further comprising a silicide under the contact plug. 4 . The semiconductor device of claim 3 , wherein a bottom surface of the silicide comprises an arc. 5 . The semiconductor device of claim 4 , wherein the epitaxial layer comprises silicon phosphide.
Assignees
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Classifications
the processing being a planarisation of insulating layers · CPC title
Aspects related to lithography, isolation or planarisation of the conductor · CPC title
Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title
of electrodes ohmically coupled to a semiconductor · CPC title
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2017200824A1 cover?
- A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in whi…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7845. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 13 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).