Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate
US-10825718-B2 · Nov 3, 2020 · US
of silicon-on-insulator structures
of silicon-on-insulator structures · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10P36/07 |
| Official title | {of silicon-on-insulator structures} |
| Display label | of silicon-on-insulator structures |
| Total patents | 171 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 7 |
| 2016 | 8 |
| 2017 | 10 |
| 2018 | 10 |
| 2019 | 15 |
| 2020 | 11 |
| 2021 | 32 |
| 2022 | 26 |
| 2023 | 17 |
| 2024 | 18 |
| 2025 | 14 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic appliance including the semiconductor device, the display device, and the display module
US-2020313002-A1 · Oct 1, 2020 · US
Healing method before transfer of a semiconducting layer
US-2020219719-A1 · Jul 9, 2020 · US
Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic appliance including the semiconductor device, the display device, and the display module
US-10693014-B2 · Jun 23, 2020 · US
Managed Substrate Effects for Stabilized SOI FETs
US-2020176252-A1 · Jun 4, 2020 · US
Epitaxy substrate and method of manufacturing the same
US-2020075328-A1 · Mar 5, 2020 · US
Method for manufacturing bonded SOI wafer
US-10566196-B2 · Feb 18, 2020 · US
Managed substrate effects for stabilized SOI FETs
US-10546747-B2 · Jan 28, 2020 · US
Radio frequency silicon on insulator structure with superior performance, stability, and manufacturability
US-2020020571-A1 · Jan 16, 2020 · US
Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
US-2020020766-A1 · Jan 16, 2020 · US
Method of fabrication of a semiconductor element comprising a highly resistive substrate
US-10510531-B2 · Dec 17, 2019 · US
High resistivity silicon-on-insulator substrate comprising an isolation region
US-10475695-B2 · Nov 12, 2019 · US
Structure and Method for Embedded Gettering in a Silicon On Insulator Wafer
US-2019326128-A1 · Oct 24, 2019 · US
Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate
US-2019214294-A1 · Jul 11, 2019 · US
Structure for radio-frequency applications
US-10347597-B2 · Jul 9, 2019 · US
Methods and apparatus for gettering impurities in semiconductors
US-2019189464-A1 · Jun 20, 2019 · US
Process for the manufacture of a semiconductor element comprising a layer for trapping charges
US-10297464-B2 · May 21, 2019 · US
Semiconductor wafer and semiconductor wafer fabrication method
US-2019148127-A1 · May 16, 2019 · US
Bonded semiconductor wafer and method for manufacturing bonded semiconductor wafer
US-10283401-B2 · May 7, 2019 · US
Managed substrate effects for stabilized SOI FETs
US-10276371-B2 · Apr 30, 2019 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10P36/07?
- CPC H10P36/07 is the Cooperative Patent Classification code for “of silicon-on-insulator structures.”
- How many patents are filed under CPC H10P36/07 (of silicon-on-insulator structures)?
- Our database includes 171 publications tagged with this CPC code.
- Is patent activity under CPC H10P36/07 growing?
- Publication counts under this code: 18 in 2024 vs 14 in 2025 (latest complete years).