Managed substrate effects for stabilized SOI FETs

Patent metadata

Field	Value
Publication number	US-10276371-B2
Application number	US-201715600588-A
Country	US
Kind code	B2
Filing date	May 19, 2017
Priority date	May 19, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

First claim

What is claimed is:

1. An integrated circuit formed from a silicon-on-insulator (SOI) substrate having a trap rich layer formed on the substrate, at least one modified region fabricated within the trap rich layer that is more conductive than the trap rich layer, an insulator layer formed on the trap rich layer, and an active layer formed on the insulator layer, wherein circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry is fabricated in and/or on the active layer above at least one of the modified regions.

2. The invention of claim 1 , wherein circuitry that can benefit from the characteristics of the trap rich layer is fabricated in and/or on the active layer above the trap rich layer.

3. The invention of claim 1 , wherein each modified region is fabricated by implanting or diffusing a dopant into a selected area of the trap rich layer before the insulator layer is formed on the trap rich layer.

4. The invention of claim 1 , wherein each modified region is fabricated by implanting a dopant into a selected area of the trap rich layer after the insulator layer is formed on the trap rich layer.

5. The invention of claim 1 , wherein each modified region is fabricated by laser annealing a selected area of the trap rich layer after the insulator layer is formed on the trap rich layer.

6. The invention of claim 1 , wherein each modified region is fabricated by implanting a dopant into a selected area of the trap rich layer after forming the active layer.

7. The invention of claim 1 , wherein each modified region is fabricated by laser annealing a selected area of the trap rich layer after forming the active layer.

8. The invention of claim 1 , further including at least one substrate contact near at least one area of circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry.

9. The invention of claim 1 , further including at least a partial ring of substrate contacts around at least one area of circuitry susceptible to an accumulated charge that would result from the interaction of an underlying trap rich region and transient changes of state of such circuitry.

10. The invention of claim 1 , wherein the substrate is a high resistivity substrate.

Assignees

• Psemi Corp

Inventors

• Englekirk Robert Mark
• Bargroff Keith
• Murphy Christopher C
• Ranta Tero Tapio
• Willard Simon Edward

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P36/07

  of silicon-on-insulator structures · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P90/192

  irregularly shaped charge trapping layers · CPC title