Method for manufacturing bonded SOI wafer

Patent metadata

Field	Value
Publication number	US-10566196-B2
Application number	US-201615572769-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Jun 9, 2015
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 Ω·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.

First claim

The invention claimed is:

1. A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer each composed of a silicon single crystal with an insulator film being interposed therebetween, the method comprising at least the steps of:
depositing a polycrystalline silicon layer on a surface to be bonded of the base wafer;
polishing a surface of the polycrystalline silicon layer;
forming the insulator film on a surface to be bonded of the bond wafer;
bonding the bond wafer and the polished surface of the polycrystalline silicon layer of the base wafer with the insulator film being interposed therebetween;
thinning the bond wafer that has been bonded to form an SOI layer; wherein
a silicon single crystal wafer having a resistivity of 100 Ω·cm or more is used as the base wafer,
the step of depositing the polycrystalline silicon layer includes a stage of previously forming an oxide film having a thickness thicker than 10 nm and less than or equal to 30 nm on the surface of the base wafer on which the polycrystalline silicon layer is to be deposited, and
the polycrystalline silicon layer is deposited at 1050° C. or more and 1200° C. or less.

2. The method for manufacturing a bonded SOI wafer according to claim 1 , wherein, after forming the oxide film and before depositing the polycrystalline silicon layer, a heat treatment is performed at 1050° C. or more and 1200° C. or less for 1 second or more and 60 seconds or less under a hydrogen-containing atmosphere.

3. The method for manufacturing a bonded SOI wafer according to claim 2 , wherein the heat treatment under the hydrogen-containing atmosphere and the depositing the polycrystalline silicon layer are successively performed with one apparatus.

4. The method for manufacturing a bonded SOI wafer according to claim 1 , wherein the thickness of the oxide film is 15 nm or more and less than or equal to 30 nm.

5. The method for manufacturing a bonded SOI wafer according to claim 1 , wherein the polycrystalline silicon layer is deposited at 1100° C. or more and 1200° C. or less.

Assignees

• Shinetsu Handotai Kk

Inventors

• Kobayashi Norihiro
• Ishikawa Osamu
• Meguro Kenji
• Wakabayashi Taishi
• Oonishi Hiroyuki

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P36/07

  of silicon-on-insulator structures · CPC title

• H10P90/1918

  including charge trapping layers, e.g. polycrystalline materials · CPC title