Structure for radio-frequency applications

Patent metadata

Field	Value
Publication number	US-10347597-B2
Application number	US-201515500721-A
Country	US
Kind code	B2
Filing date	Jul 3, 2015
Priority date	Aug 1, 2014
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.

First claim

The invention claimed is:

1. A structure for radiofrequency applications comprising:
a support substrate of high-resistivity silicon comprising a non-doped lower part and a p-type doped upper part, the p-typed doped upper part formed to a depth D of less than 1 micro in the support substrate; and
a mesoporous trapping layer of silicon formed in the p-type doped upper part of the support substrate, the mesoporous trapping layer having a porosity rate of between 20% and 60% such that the mesoporous trapping layer traps inversion charges susceptible to be generated in the non-doped lower part and the non-doped lower part retains a high and stable resistivity level.

2. The structure of claim 1 , wherein the mesoporous trapping layer has pores with a diameter of between 2 nm and 50 nm.

3. The structure of claim 2 , wherein the resistivity of the non-doped lower part of the support substrate is greater than 1000 ohm·cm.

4. The structure of claim 1 , wherein an active layer is disposed over the mesoporous trapping layer.

5. The structure of claim 4 , wherein the active layer compromises a semiconductive material.

6. The structure of claim 4 , wherein the active layer compromises a piezoelectric material.

7. The structure of claim 4 , wherein the active layer comprises at least one material selected from the group consisting of: silicon, silicon carbide, silicon germanium, lithium niobate, lithium tantalate, quartz, and aluminum nitride.

8. The structure of claim 4 , wherein the thickness of the active layer is between 10 nm and 50 μm.

9. The structure of claim 4 , wherein a dielectric layer is disposed between the mesoporous trapping layer and the active layer.

10. The structure of claim 9 , wherein the dielectric layer comprises at least one material selected from the group consisting of: silicon dioxide, silicon nitride, and aluminum oxide.

11. The structure of claim 10 , wherein the dielectric layer is between 10 nm and 6 μm.

12. The structure of claim 4 , wherein at least one microelectronic device is present on or in the active layer, the microelectronic device being a switching circuit or an antenna tuning circuit or a radiofrequency power amplification circuit.

13. The structure of claim 4 , wherein at least one microelectronic device is present on or in the active layer, the microelectronic device comprising a plurality of active components and a plurality of passive components.

14. The structure of claim 4 , wherein at least one microelectronic device is present on or in the active layer, the microelectronic device comprising at least one control element and one MEMS switching element comprising a microswitch with ohmic contact or a capacitive microswitch.

15. The structure of claim 4 , wherein at least one microelectronic device is present on or in the active layer, the microelectronic device comprising a radiofrequency filter operating by bulk or surface acoustic wave propagation.

16. The structure of claim 1 , wherein the resistivity of the non-doped lower part of the support substrate is greater than 1000 ohm·cm.

17. The structure of claim 1 , wherein an active layer is arranged on the mesoporous trapping layer.

18. The structure of claim 9 , wherein the dielectric layer is between 10 nm and 6 μm.

Assignees

• Soitec Silicon On Insulator

Inventors

• Kononchuk Oleg
• Van Den Daele William
• Desbonnets Eric

Classifications

• H10P36/07 Primary

  of silicon-on-insulator structures · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914 Primary

  using bonding · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P90/1918

  including charge trapping layers, e.g. polycrystalline materials · CPC title