Process for the manufacture of a semiconductor element comprising a layer for trapping charges

Patent metadata

Field	Value
Publication number	US-10297464-B2
Application number	US-201615577133-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Jun 9, 2015
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor element, the method comprising:
providing a substrate comprising a support, a charge trapping layer on the support, an insulating layer on the charge trapping layer and a superficial semiconductor layer on the insulating layer;
applying a rapid heat treatment of the substrate comprising the charge-trapping layer, the rapid heat treatment damaging an RF characteristic of the substrate; and
following the rapid heat treatment, applying a healing heat treatment of the substrate between 700° C. and 1,100° C. for a period of time of at least 15 seconds to improve the damaged RF characteristic of the substrate.

2. The method of claim 1 , wherein the healing heat treatment is carried out in a neutral or reducing atmosphere.

3. The method of claim 2 , wherein the healing heat treatment comprises an annealing at 950° C. for one hour.

4. The method of claim 2 , wherein the healing heat treatment comprises an annealing at 950° C. for one hour.

5. The method of claim 4 , wherein the rapid heat treatment stage is carried out in a rapid heat treatment system.

6. The method of claim 5 , wherein the healing heat treatment is carried out in situ in the rapid heat treatment system.

7. The method of claim 6 , wherein the healing heat treatment comprises an annealing at 950° C. for a period of time of between 15 seconds and 2 minutes.

8. The method of claim 6 , wherein the healing heat treatment is carried out by controlling a fall in temperature on completion of the rapid heat treatment at 40° C./s or less.

9. The method of claim 4 , wherein the rapid heat treatment stage is carried out in a rapid heat treatment system.

10. The method of claim 1 , wherein the rapid heat treatment comprises exposing the substrate to a treatment atmosphere for a maximum period of time of 2 minutes at a plateau temperature of between 1,125° C. and 1,250° C.

11. The method of claim 1 , wherein the semiconductor element comprises an RF device.

12. The method of claim 1 , wherein the semiconductor element comprises a silicon-on-insulator wafer having a diameter of at least 200 mm.

13. The method of claim 1 , wherein the charge-trapping layer comprises a polycrystalline silicon layer.

14. The method of claim 1 , wherein the RF characteristic of the substrate is evaluated by a second harmonic distortion measurement.

Assignees

• Soitec Silicon On Insulator

Inventors

• Broekaart Marcel
• Capello Luciana
• Bertrand Isabelle
• Colombet Norbert

Classifications

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P72/0436

  mainly by radiation · CPC title

• H10P34/422

  using incoherent radiation · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title