Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells

Patent metadata

Field	Value
Publication number	US-9761575-B1
Application number	US-201615395800-A
Country	US
Kind code	B1
Filing date	Dec 30, 2016
Priority date	Apr 4, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of short-circuit failure modes, including at least one chamfer-short-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one TS-short-related failure mode.

First claim

What we claim in this application is:

1. A monolithic integrated circuit (1C) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V0) layer, a first wiring (M1) layer, a second wiring (M2) layer, and an M1-to-M2 via (VI) layer, said 1C comprising at least:
(i) a plurality of logic cells selected from a standard cell library in which each logic cell has a height, supply rail configuration, and GATE pitch (CPP) configured for abutted instantiation with other logic cells in the library; and,
(ii) a plurality of at least four different, non-contact electrical measurement (NCEM)-enabled fill cells, each of said NCEM-enabled fill cells having a height, supply rail configuration, and CPP configured for abutted instantiation with logic cells in the standard cell library, said plurality of NCEM-enabled fill cells including:
(a) at least one chamfer-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test area patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves a via chamfering;
(b) at least one AACNT-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves the AACNT layer;
(c) at least one GATE-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves the GATE layer; and,
(d) at least one TS-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that involves the TS layer.

2. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V0-AACNT-chamfer-short-configured, NCEM-enabled fill cell.

3. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V3-M3-chamfer-short-configured, NCEM-enabled fill cell.

4. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cell.

5. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V1-M1-via-chamfer-short-configured, NCEM-enabled fill cell.

6. A monolithic IC, as defined in claim 1 , wherein the at least one chamfer-short-configured, NCEM-enabled fill cell comprises a V2-M2-via-chamfer-short-configured, NCEM-enabled fill cell.

7. A monolithic IC, as defined in claim 1 , wherein the at least one AACNT-short-configured, NCEM-enabled fill cell comprises a V0-AACNT-chamfer-short-configured, NCEM-enabled fill cell.

8. A monolithic IC, as defined in claim 1 , wherein the at least one AACNT-short-configured, NCEM-enabled fill cell comprises an AACNT-tip-to-tip-short-configured, NCEM-enabled fill cell.

9. A monolithic IC, as defined in claim 1 , wherein the at least one AACNT-short-configured, NCEM-enabled fill cell comprises at least one of:
an AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cell;
a GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cell;
an AACNT-tip-to-side-short-configured, NCEM-enabled fill cell;
an AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cell;
a GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cell;
an AACNT-side-to-side-short-configured, NCEM-enabled fill cell;
an AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cell;
an AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cell;
a GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cell;
an AACNT-diagonal-short-configured, NCEM-enabled fill cell;
an AACNT-AA-diagonal-short-configured, NCEM-enabled fill cell;
a GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cell;
a GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cell;
an AACNT-corner-short-configured, NCEM-enabled fill cell;
an AACNT-AA-corner-short-configured, NCEM-enabled fill cell;
a GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cell;
a GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cell;
an M1-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cell; and/or,
an AACNT-via-chamfer-short-configured, NCEM-enabled fill cell.

10. A monolithic IC, as defined in claim 1 , wherein the at least one GATE-short-configured, NCEM-enabled fill cell comprises a TS-GATE-side-to-side-short-configured, NCEM-enabled fill cell.

11. A monolithic IC, as defined in claim 1 , wherein the at least one GATE-short-configured, NCEM-enabled fill cell comprises a GATE-tip-to-tip-short-configured, NCEM-enabled fill cell.

12. A monolithic IC, as defined in claim 1 , wherein the at least one GATE-short-configured, NCEM-enabled fill cell comprises at least one of:
a GATECNT-GATE-tip-to-tip-short-configured, NCEM-enabled fill cell;
a GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cell;
a GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cell;
an AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cell;
a GATE-side-to-side-short-configured, NCEM-enabled fill cell;
a GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cell;
a GATE-diagonal-short-configured, NCEM-enabled fill cell;
a GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cell;
a GATECNT-GATE-diagonal-short-configured, NCEM-enabled fill cell;
a GATE-corner-short-configured, NCEM-enabled fill cell;
a GATECNT-GATE-corner-short-configured, NCEM-enabled fill cell;
a GATE-AA-interlayer-overlap-short-configured, NCEM-enabled fill cell;
a GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell;
a GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cell; and/or,
a V0-GATE-interlayer-overlap-short-configured, NCEM-enabled fill cell.

13. A monolithic IC, as defined in claim 1 , wherein the at least one TS-short-configured, NCEM-enabled fill cell comprises a GATECNT-TS-corner-short-configured, NCEM-enabled fill cell.

14. A monolithic IC, as defined in claim 1 , wherein the at least one TS-short-configured, NCEM-enabled fill cell comprises TS-GATE-side-to-side-short-configured, NCEM-enabled fill cell.

15. A monolithic IC, as defined in claim 1 , wherein the at least one TS-short-configured, NCEM-enabled fill cell comprises at least one of:
an AACNT-TS-tip-to-tip-short-configured, NCEM-enabled fill cell;
a TS-tip-to-tip-short-configured, NCEM-enabled fill cell;
a TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cell;
a GATECNT-AACNT-TS-tip-to-side-short-configured, NCEM-enabled fill cell;
a TS-diagonal-short-configured, NCEM-enabled fill cell;
a GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell;
a GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell; and/or,
a V0-TS-interlayer-overlap-short-configured, NCEM-enabled fill cell.

16. A monolithic IC, as defined in claim 1 , wherein at least two of the (b) at least one AACNT-short-configured, (c)

Assignees

• Pdf Solutions Inc

Inventors

• Lam Stephen
• Ciplickas Dennis
• Brozek Tomasz
• Cheng Jeremy
• Comensoli Simone
• De Indranil
• Doong Kelvin
• Eisenmann Hans
• Fiscus Timothy
• Haigh Jonathan
• Hess Christopher
• Kibarian John
• Lee Sherry
• Liao Marci
• Lin Sheng-Che
• Matsuhashi Hideki
• Michaels Kimon
• O'Sullivan Conor
• Rauscher Markus
• Rovner Vyacheslav
• Strojwas Andrzej
• Strojwas Marcin
• Taylor Carl
• Vallishayee Rakesh
• Weiland Larg
• Yokoyama Nobuharu

Classifications

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title