Metal track cutting in standard cell layouts

Patent metadata

Field	Value
Publication number	US-9837398-B1
Application number	US-201615360168-A
Country	US
Kind code	B1
Filing date	Nov 23, 2016
Priority date	Nov 23, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

First claim

What is claimed:

1. An integrated circuit layout, comprising:
a standard cell;
a metal layer in the standard cell, the metal layer comprising a plurality of substantially parallel metal tracks placed in the standard cell, wherein the metal tracks extend a width of the standard cell;
one or more active sections defined in the metal tracks;
one or more inactive sections defined in the metal tracks, wherein the inactive sections of the metal tracks are defined as sections of the metal tracks outside of the active sections; and
at least one cut placed in at least one inactive region on at least one metal track, wherein the at least one cut is placed to electrically isolate a portion of the at least one metal track in the at least one inactive region from an adjacent portion of the at least one metal track.

2. The integrated circuit layout of claim 1 , wherein the metal tracks extend from a first side of the standard cell to a second side of the standard cell, the first side being opposite the second side.

3. The integrated circuit layout of claim 1 , wherein the active sections are defined by a plurality of cuts placed on the metal tracks.

4. The integrated circuit layout of claim 1 , wherein at least one active section on at least one metal track is defined by cuts placed on each end of the at least one active section.

5. The integrated circuit layout of claim 4 , wherein at least one inactive section on the at least one metal track comprises a section of the at least one metal track on the other side of the cut placed on an end of the at least one active section.

6. The integrated circuit layout of claim 1 , wherein the active sections are defined by a plurality of connections placed on the metal tracks.

7. The integrated circuit layout of claim 6 , wherein at least one connection comprises a connection to another layer in the standard cell.

8. The integrated circuit layout of claim 1 , wherein at least one active section on at least one metal track is defined by connections placed on each end of the at least one active section.

9. The integrated circuit layout of claim 8 , wherein at least one inactive section on the at least one metal track comprises a section of the at least one metal track on the other side of the connection placed on an end of the at least one active section.

10. The integrated circuit layout of claim 1 , wherein the at least one cut placed in the at least one inactive region on the at least one metal track is placed as close to an adjacent active region of the at least one metal track as allowed by design rules for the standard cell.

11. The integrated circuit layout of claim 1 , wherein the at least one cut placed in the at least one inactive region on the at least one metal track is placed at a boundary of the standard cell.

12. A computer implemented method, comprising:
placing, by a place-and-route tool, executed using a computer processor, in dependence upon a netlist for an integrated circuit, a standard cell in a layout of the integrated circuit, wherein placing the standard cell comprises:
placing a metal layer in the layout, the metal layer comprising a plurality of substantially parallel metal tracks placed in the standard cell, wherein the metal tracks extend a width of the standard cell;
defining one or more active sections in the metal tracks;
defining one or more inactive sections in the metal tracks, wherein the inactive sections of the metal tracks are defined as sections of the metal tracks outside of the active sections; and
placing at least one cut in at least one inactive region on at least one metal track, wherein the at least one cut is placed to electrically isolate a portion of the at least one metal track in the at least one inactive region from an adjacent portion of the at least one metal track.

13. The computer implemented method of claim 12 , wherein the metal tracks extend from a first side of the standard cell to a second side of the standard cell, the first side being opposite the second side.

14. The computer implemented method of claim 12 , further comprising placing an additional cut on each end of at least one active section on at least one metal track to define the at least one active section.

15. The computer implemented method of claim 12 , further comprising placing a connection on each end of at least one active section on at least one metal track to define the at least one active section.

16. The computer implemented method of claim 15 , wherein the connection on at least one end of the at least one active section comprises a connection to another layer in the standard cell.

17. The computer implemented method of claim 12 , further comprising generating, by the place-and-route tool based on the integrated circuit layout, one or more computer instructions for use in integrated circuit fabrication.

18. A non-transitory computer readable storage medium storing a plurality of instructions which, when executed, generate an integrated circuit layout that comprises:
a standard cell;
a metal layer in the standard cell, the metal layer comprising a plurality of substantially parallel metal tracks placed in the standard cell, wherein the metal tracks extend a width of the standard cell;
one or more active sections defined in the metal tracks;
one or more inactive sections defined in the metal tracks, wherein the inactive sections of the metal tracks are defined as sections of the metal tracks outside of the active sections; and
at least one cut placed in at least one inactive region on at least one metal track, wherein the at least one cut is placed to electrically isolate a portion of the at least one metal track in the at least one inactive region from an adjacent portion of the at least one metal track.

19. The non-transitory computer readable storage medium of claim 18 , wherein the plurality of instructions comprises design rules for the standard cell that define an allowable distance between the at least one cut and an adjacent active region of the at least one metal track for placement of the at least one cut.

20. The non-transitory computer readable storage medium of claim 18 , wherein the plurality of instructions comprises design rules for the standard cell that place the at least one cut placed at a boundary of the standard cell.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Rowhani Omid
• Cain Jason P
• Cordos Ioan
• Sherriff Michael Davinson
• Dao Hoang Q

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5072

  Physics · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic