Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture

Patent metadata

Field	Value
Publication number	US-9704760-B2
Application number	US-201514749614-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jun 24, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.

First claim

What is claimed is:

1. A method of forming logic cell contacts, said method comprising:
forming gates on fins defining field effect transistors (FETs) on a semiconductor wafer, at least one gate defining a finFET pair including a first type FET and a second type FET;
forming a plug of an insulating material between the gates in selected FET pairs, each said plug isolating FET pair gates from each other;
forming a contact dielectric layer on said semiconductor wafer;
opening contacts through said contact dielectric layer to one side of each said plug, each contact partially exposing ends of an isolated pair of FET gates and exposing a gate sidewall of each said FET gate of each said pair; and
filling the open contacts with conductive material, said conductive material forming gate sidewall contacts to respective said pairs, said gate sidewall contacts stitching said respective gate pairs together, wherein said gates are replacement metal gates (RMG), said plugs and said gate sidewalls are nitride, and said contact dielectric layer is oxide.

2. A method of forming logic cell contacts as in claim 1 , wherein opening contacts comprises:
forming a contact pattern on said contact dielectric layer, said contact pattern defining an offset contact at each said plug, each said offset contact overlapping the plug and a cut end corner of both gates of a respective FET pair;
etching said offset contact pattern through said contact dielectric layer to said gates with a first etchant, each said offset contact exposing an upper surface of said plugs, a portion of each overlapped gate and overlapped portions of gate sidewalls; and
etching through said offset contact pattern with a second etchant, said second etchant etching exposed said plugs and overlapped gate sidewall portions.

3. A method of forming logic cell contacts as in claim 2 , wherein contacts in said contact pattern have a regular shape, and filled offset contacts have an irregular cross section.

4. A method of forming logic cell contacts as in claim 1 , wherein said first type is P-type and said second type is N-type, and filling said open contacts comprises:
forming a metal layer on said semiconductor wafer, said metal layer filling said open contacts with metal; and
removing horizontal portions of said metal layer, remaining metal forming said gate sidewall contacts.

5. A method of forming a CMOS integrated circuit (IC) chip with one or more logic cells having gate sidewall contacts formed as in claim 4 , said method further comprising forming a wiring layer on the gate sidewall contact layer, wires on said wiring layer being oriented in a single direction and connecting to said gate sidewall contacts without jogging from said single direction.

6. A method of forming an integrated circuit (IC) chip with one or more logic cells having gate sidewall contacts formed as in claim 4 , said method further comprising:
forming a via layer on said wiring layer, at least one via connecting to logic cell directly above a gate sidewall contact; and
forming one or more wiring layers above said via layer, said one or more wiring layers connecting logic cells together.

7. A method of forming logic cell contacts as in claim 1 , wherein forming said replacement metal gates on fins comprises:
forming sacrificial gates at RMG locations;
removing said sacrificial gates;
forming said nitride gate sidewalls; and
forming metal gates between said nitride gate sidewalls, a plurality of finFET pairs each including one said PFET, one said NFET and being formed by a common one of said metal gates.

8. A method of forming logic cell contacts as in claim 7 , wherein forming plugs comprises:
forming a cut pattern on said semiconductor wafer, said cut pattern selecting said FET pairs for separation;
etching metal between gates for selected said FET pairs, etched said metal separating PFETs from NFETS in the pairs; and
filling space between separated gates with said insulating material.

9. A method of forming logic cell contacts as in claim 8 , wherein said nitride gate sidewalls remain unetched by said cut pattern and by etching metal between FETs, forming the plugs filling a gap between said gates and said nitride gate sidewalls with said insulating material.

10. A method of forming a CMOS integrated circuit (IC) chip with one or more logic cells, said method comprising:
forming fins on a semiconductor wafer;
forming gates on said fins defining field effect transistors (FETs), at least one gate defining a FET pair including a PFET and an NFET;
forming a plug of a first dielectric between the gates in selected FET pairs, each said plug isolating FET pair gates from each other;
forming a contact dielectric layer on said semiconductor wafer;
opening contact holes offset to one side of each said plug, each contact hole partially exposing one respective said plug and partially exposing isolated respective said FET pair gates;
exposing sidewalls of said FET pair gates through respective contact holes;
filling the open contact holes with conductive material, said conductive material forming gate sidewall contacts to respective said pairs, said gate sidewall contacts stitching said respective pairs together;
forming a wiring layer on said gate contact dielectric layer, wires being oriented in a single direction on said wiring layer and connecting to said gate sidewall contacts without jogging from said single direction; and
forming at least one conductive via directly on a gate sidewall contact in a logic cell, wherein said gates are replacement metal gates (RMG), said plugs and said gate sidewalls are nitride, and said contact dielectric layer is oxide.

11. A method of forming an IC chip as in claim 10 , wherein forming plugs comprises:
forming a cut pattern on said semiconductor wafer, said cut pattern selecting said FET pairs for separation;
etching metal between gates for selected said FET pairs, etched said metal separating PFETs from NFETs in the pairs; and
filling space between separated gates with said insulating material.

12. A method of forming an IC chip as in claim 11 , wherein said nitride gate sidewalls remain unetched by said cut pattern and by etching metal between FETs, forming the plugs filling a gap between said gates and said nitride gate sidewalls with said insulating material.

13. A method of forming an IC chip as in claim 10 , wherein opening contact holes comprises:
forming a contact pattern defining contacts offset at each said plug, each said contact overlapping a single cut end corner of both gates of a respective FET pair; and
etching said contact holes pattern through said contact dielectric layer to said gates with a first etchant, each said offset contact hole exposing an upper surface of said plugs, a corner portion of each overlapped gate and overlapped portions of gate sidewalls.

14. A method of forming an IC chip as in claim 10 , wherein exposing gate sidewalls comprises etching through said offset contact holes with a second etchant, said second etchant etching exposed said plugs and overlapped gate sidewall portions.

15. A method of forming an IC chip as in claim 10 , wherein filling the open contact holes comprises:
forming a metal layer on said semiconductor wafer, said metal layer filling said open contact holes and contacting exposed gate sidewalls; and
removing horizontal portions of said metal layer, remaining metal forming said gate sidewall contacts.

16. A method of forming an IC chip as in claim 10 , said method further comprising forming one or more wiring layers above said via layer, said one

Assignees

• IBM

Inventors

• Ok Injo
• Pranatharthiharan Balasubramanian
• Seo Soon-Cheon
• Surisetty Charan V

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title