Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including metal island open configured fill cells

Patent metadata

Field	Value
Publication number	US-9766970-B1
Application number	US-201715635259-A
Country	US
Kind code	B1
Filing date	Jun 28, 2017
Priority date	Apr 4, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens.

First claim

What is claimed in this application is:

1. A monolithic integrated circuit (IC) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V 0 ) layer, a first wiring (M 1 ) layer, a second wiring (M 2 ) layer, and an M 1 -to-M 2 via (V 1 ) layer, said IC comprising at least:
(i) a first design of experiments (DOE) that includes at least first and second non-contact electrical measurement (NCEM)-enabled fill cells, each of the first and second NCEM-enabled fill cells configured in a standard cell form, with first and second supply rails that extend horizontally across the cell and uniformly spaced GATE stripes that extend vertically across the cell, each of the first and second NCEM-enabled fill cells further including test area patterning that comprises at least first and second features, arranged in a merged-via open configuration, wherein the first feature is electrically connected to an NCEM pad and the second feature is electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area patterning using a non-contact (NC) measurement at the NCEM pad, the first and second NCEM-enabled fill cells further having at least one patterning difference that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell; and,
(ii) a second DOE that includes at least first and second NCEM-enabled fill cells, each of the first and second NCEM-enabled fill cells configured in a standard cell form, with first and second supply rails that extend horizontally across the cell and uniformly spaced GATE stripes that extend vertically across the cell, each of the first and second NCEM-enabled fill cells further including test area patterning that comprises at least first and second features, arranged in a metal island open configuration, wherein the first feature is electrically connected to an NCEM pad and the second feature is electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area patterning using a NC measurement at the NCEM pad, the first and second NCEM-enabled fill cells further having at least one patterning difference that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell;
wherein all of the NCEM-enabled fill cells in the first and second DOEs are configured in a compatible standard cell form, with identical spacing between the first and second supply rails and identical spacing between adjacent GATE stripes.

2. A monolithic IC, as defined in claim 1 , wherein the IC is in the form of a semiconductor wafer.

3. A monolithic IC, as defined in claim 1 , wherein the IC is in the form of a semiconductor die.

4. A monolithic IC, as defined in claim 1 , wherein each of the first and second DOEs includes at least three different NCEM-enabled fill cells.

5. A monolithic IC, as defined in claim 1 , wherein each of the first and second DOEs includes at least five different NCEM-enabled fill cells.

6. A monolithic IC, as defined in claim 1 , wherein at least one of the first and/or second DOE(s) includes at least ten different NCEM-enabled fill cells.

7. A monolithic IC, as defined in claim 1 , wherein at least one of the first and/or second DOE(s) includes at least twenty different NCEM-enabled fill cells.

8. A monolithic IC, as defined in claim 1 , wherein the merged-via-open-configured, NCEM-enabled fill cells of the first DOE comprise V 0 -merged-via-open-configured, NCEM-enabled fill cells.

9. A monolithic IC, as defined in claim 1 , wherein the IC further includes at least a third wiring (M 3 ) layer, an M 2 -to-M 3 via (V 2 ) layer, a fourth wiring (M 4 ) layer, an M 3 -to-M 4 via (V 3 ) layer, a fifth wiring (M 5 ) layer, and an M 4 -to-M 5 via (V 4 ) layer, and the IC further includes at least one additional NCEM-enabled fill cell selected from the list consisting of:
AA-tip-to-tip-short-configured, NCEM-enabled fill cells;
AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;
AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cells;
TS-tip-to-tip-short-configured, NCEM-enabled fill cells;
GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;
GATECNT-tip-to-tip-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;
M 1 -tip-to-tip-short-configured, NCEM-enabled fill cells;
V 0 -tip-to-tip-short-configured, NCEM-enabled fill cells;
M 1 -V 0 -tip-to-tip-short-configured, NCEM-enabled fill cells;
V 1 -M 1 -tip-to-tip-short-configured, NCEM-enabled fill cells;
V 1 -tip-to-tip-short-configured, NCEM-enabled fill cells;
M 2 -tip-to-tip-short-configured, NCEM-enabled fill cells;
M 2 -V 1 -tip-to-tip-short-configured, NCEM-enabled fill cells;
V 2 -M 2 -tip-to-tip-short-configured, NCEM-enabled fill cells;
M 3 -tip-to-tip-short-configured, NCEM-enabled fill cells;
V 2 -tip-to-tip-short-configured, NCEM-enabled fill cells;
M 3 -V 2 -tip-to-tip-short-configured, NCEM-enabled fill cells;
AA-tip-to-side-short-configured, NCEM-enabled fill cells;
AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;
AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cells;
GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;
TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;
M 1 -tip-to-side-short-configured, NCEM-enabled fill cells;
V 0 -tip-to-side-short-configured, NCEM-enabled fill cells;
M 1 -V 0 -tip-to-side-short-configured, NCEM-enabled fill cells;
V 1 -M 1 -tip-to-side-short-configured, NCEM-enabled fill cells;
V 1 -tip-to-side-short-configured, NCEM-enabled fill cells;
M 2 -tip-to-side-short-configured, NCEM-enabled fill cells;
M 2 -V 1 -tip-to-side-short-configured, NCEM-enabled fill cells;
V 2 -M 2 -tip-to-side-short-configured, NCEM-enabled fill cells;
M 3 -tip-to-side-short-configured, NCEM-enabled fill cells;
V 2 -tip-to-side-short-configured, NCEM-enabled fill cells;
M 3 -V 2 -tip-to-side-short-configured, NCEM-enabled fill cells;
AA-side-to-side-short-configured, NCEM-enabled fill cells;
AACNT-side-to-side-short-configured, NCEM-enabled fill cells;
AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cells;
AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;
GATE-side-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;
TS-GATE-side-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-side-to-side-short-configured, NCEM-enabled fill cells;
GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cells;
M 1 -side-to-side-short-configured, NCEM-enabled fill cells;
V 0 -side-to-side-short-configured, NCEM-enabled fill cells;
M 1 -V 0 -side-to-side-short-configured, NCEM-enabled fill cells;
V 1 -M 1 -side-to-side-short-configured, NCEM-enabled fill cells;
V 1 -side-to-side-short-configured, NCEM-enabled fill cells;
M 2 -side-to-side-short-configured, NCEM-enabled fill cells;
M 2 -V 1 -side-to-side-short-configured, NCEM-enabled fill cells;
V 2 -M 2 -side-to-side-short-configured

Assignees

• Pdf Solutions Inc

Inventors

• Lam Stephen
• Ciplickas Dennis
• Brozek Tomasz
• Cheng Jeremy
• Comensoli Simone
• De Indranil
• Doong Kelvin
• Eisenmann Hans
• Fiscus Timothy
• Haigh Jonathan
• Hess Christopher
• Kibarian John
• Lee Sherry
• Liao Marci
• Lin Sheng-Che
• Matsuhashi Hideki
• Michaels Kimon
• O'Sullivan Conor
• Rauscher Markus
• Rovner Vyacheslav
• Strojwas Andrzej
• Strojwas Marcin
• Taylor Carl
• Vallishayee Rakesh
• Weiland Larg
• Yokoyama Nobuharu

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/30

  Circuit design · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title