Method, apparatus, and system for improved cell design having unidirectional metal layout architecture

Patent metadata

Field	Value
Publication number	US-2017323902-A1
Application number	US-201615149066-A
Country	US
Kind code	A1
Filing date	May 6, 2016
Priority date	May 6, 2016
Publication date	Nov 9, 2017
Grant date	—

Abstract

At least one method, apparatus and system disclosed involves circuit layout for comprising a unidirectional metal layout. A first trench silicide (TS) formation is formed in a first active area of a functional cell. A first CA formation if formed above the first TS formation. A first vertical metal formation is formed in a first metal layer from the first active area to a second active area of the functional cell. The first vertical metal formation is formed offset relative to, and in contact with, the CA formation. A second TS formation is formed in a second active area of the functional cell. A second CA formation is formed above the second TS formation. The CA formation is formed offset the first vertical metal formation, operatively coupling the first and second active areas.

First claim

1 . A method, comprising:
forming a first trench silicide (TS) formation in a first active area of a functional cell; forming a first local interconnect (CA) formation above said first TS formation; forming a first vertical metal formation in a first metal layer from said first active area to a second active area of said functional cell, wherein said first vertical metal formation is formed in contact with said CA formation such that a portion of said CA formation underlies a portion of said first vertical metal formation; forming a second TS formation in said second active area of said functional cell; forming a second CA formation above said second TS formation, wherein said second CA formation is formed in contact with the first vertical metal formation such that a portion of said second CA formation underlies a portion of said first vertical metal formation, operatively coupling said first and second active areas.

2 . The method of claim 1 , further comprising:
forming a third local interconnect (CB) formation formed offset to, and in contact with, a first gate formation; and forming a second vertical metal formation in said first metal layer offset relative to, and in contact with, said CB formation.

3 . The method of claim 2 , wherein said second vertical metal formation is formed partially offset to said first gate formation, and said first vertical metal formation is formed partially offset to a second gate formation.

4 . The method of claim 2 , further comprising:
forming a first horizontal metal formation formed in a second metal layer and in said first active area, wherein said first metal formation is coupled to said first CA formation and said first vertical metal formation by a first via; and forming a second horizontal metal formation formed in a second metal layer and in said second active area, wherein said second metal formation is coupled to said second CA formation and said second vertical metal formation by a second via.

5 . The method of claim 4 , further comprising a third horizontal metal formation formed in said second metal layer, wherein said first metal formation is coupled to said CB formation and said second vertical metal formation by a third via.

6 . The method of claim 5 , further comprising:
forming a fourth horizontal metal formation formed in said second metal layer, wherein said third horizontal metal formation is configured as a first power rail; and forming a fifth horizontal metal formation formed in said second metal layer, wherein said fourth horizontal metal formation is configured as a second power rail.

7 . The method of claim 6 , wherein
forming a first TS formation formed in said first active area, wherein said first TS formation is coupled to said fourth horizontal metal formation by a fourth via; and forming a second TS formation formed in said second active area, wherein said second TS formation is coupled to said fifth horizontal metal formation by a fifth via.

8 . The method of claim 7 , further comprising forming a functional cell using at least said first and second vertical metal formations, said first, second, third, fourth, and fifth horizontal metal formation, said first and second CA formations, said first and second CB formations, said first and second TS formations, and said first, second, third, fourth, and fifth vias.

9 . The method of claim 8 , wherein forming a functional cell comprises forming at least one of a AND cell, an OR cell, a NAND cell, a NOR cell, and XOR cell, an inverter cell, an AND-OR-INVERT (AOI) cell, and a portion of a memory cell.

10 . An integrated circuit, comprising:
a first trench silicide (TS) formation in a first active area; a first local interconnect (CA) formation above said first TS formation; a first vertical metal formation in a first metal layer spanning from said first active area to a second active area of said functional cell, wherein said first vertical metal formation is contact with said CA formation such that a portion of said CA formation underlies a portion of said first vertical metal formation; a second TS formation in a second active area of said functional cell; a second CA formation above said second TS formation, wherein said second CA formation is in contact with the first vertical metal formation such that a portion of said second CA formation underlies a portion of said first vertical metal formation, operatively coupling said first and second active areas.

11 . The integrated circuit of claim 10 , further comprising:
a third local interconnect (CB) formation formed offset to, and in contact with, a first gate formation; and a second vertical metal formation in said first metal layer formed offset relative to, and in contact with, said CB formation.

12 . The integrated circuit of claim 11 , further comprising:
a first horizontal metal formation in a second metal layer and in said first active area, wherein said first metal formation is coupled to said first CA formation and said first vertical metal formation by a first via; a second horizontal metal formation in a second metal layer and in said second active area, wherein said second metal formation is coupled to said second CA formation and said second vertical metal formation by a second via; and a third horizontal metal formation formed in said second metal layer, wherein said first metal formation is coupled to said CB formation and said second vertical metal formation by a third via.

13 . The integrated circuit of claim 12 , further comprising:
a fourth horizontal metal formation formed in said second metal layer, wherein said third horizontal metal formation is configured as a first power rail; and a fifth horizontal metal formation formed in said second metal layer, wherein said fourth horizontal metal formation is configured as a second power rail.

14 . The integrated circuit of claim 13 , further comprising:
a first TS formation formed in said first active area, wherein said first TS formation is coupled to said fourth horizontal metal formation by a fourth via; and a second TS formation formed in said second active area, wherein said second TS formation is coupled to said fifth horizontal metal formation by a fifth via.

15 . The integrated circuit of claim 10 , wherein said integrated circuit is at least one of a AND cell, an OR cell, a NAND cell, a NOR cell, and XOR cell, an inverter cell, an AND-OR-INVERT (AOI) cell, and a portion of a memory cell.

16 . A system, comprising:
a semiconductor device processing system for fabricating an integrated circuit device based upon a design comprising a functional cell; and a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system adapted to:
form a first trench silicide (TS) formation in a first active area of a functional cell;
form a first local interconnect (CA) formation above said first TS formation;
form a first vertical metal formation in a first metal layer from said first active area to a second active area of said functional cell, wherein said first vertical metal formation is formed in contact with said CA formation such that a portion of said CA formation underlies a portion of said first vertical metal formation;
form a second TS formation in a second active area of said functional cell; and
form a second CA formation above said second TS formation, wherein said CA formation is formed in contact with the first vertical metal formation such that a portion of said second

Assignees

• Globalfoundries Inc

Inventors

• Zeng Jia
• Yuan Lei
• Kye Jongwook
• Levinson Harry J

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L21/76877

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic