Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9748238-B2
Application number	US-201615206610-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Oct 1, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a device isolation layer on a substrate and defining an active pattern, the active pattern protruding upwardly from the substrate, extending in a first direction, and comprising an active fin, wherein the active fin is an upper portion of the active pattern, which is exposed by the device isolation layer;
a first gate structure and a second gate structure crossing the active pattern, extending in a second direction intersecting the first direction and spaced apart from each other in the first direction;
a dummy gate structure between the first gate structure and the second gate structure, the dummy gate structure extending in the second direction;
a first source/drain region on the active pattern between the first gate structure and the dummy gate structure;
a second source/drain region on the active pattern between the second gate structure and the dummy gate structure;
a connection contact on the dummy gate structure, the connection contact extending in the first direction to connect the first source/drain region to the second source/drain region; and
a common conductive line on the connection contact, the common conductive line configured to apply a voltage to the first and second source/drain regions through the connection contact.

2. The semiconductor device of claim 1 , wherein the device isolation layer exposes sidewalls of the active fin, and each of the first gate structure and the second gate structure cover the sidewalls of the active fin.

3. The semiconductor device of claim 2 , wherein each of the first gate structure and the second gate structure cover an upper surface of the active fin and the sidewalls of the active fin, and extend onto an upper surface of the device isolation layer.

4. The semiconductor device of claim 1 , wherein a level of an uppermost surface of the active fin is higher than that of an uppermost surface of the device isolation layer from the substrate.

5. The semiconductor device of claim 1 , wherein
the connection contact comprises:
a horizontal extension extending in the first direction; and
vertical extensions extending from the horizontal extension to top surfaces of the first and second source/drain regions, respectively, and

bottom surfaces of the vertical extensions are in contact with the first and second source/drain regions, respectively.

6. The semiconductor device of claim 5 , wherein a bottom surface of the horizontal extension is in contact with a top surface of the dummy gate structure.

7. The semiconductor device of claim 1 , wherein the active pattern comprises a first active pattern and a second active pattern which are spaced apart from each other in the second direction, and
wherein each of the first and second gate structures crosses the first and second active patterns, and the first and second source/drain regions are on the first active pattern,
The device further comprising:
a third source/drain region on the second active pattern between the first gate structure and the dummy gate structure, the third source/drain region being spaced apart from the first source/drain region in the second direction;
a fourth source/drain region on the second active pattern between the second gate structure and the dummy gate structure, the fourth source/drain region being spaced apart from the second source/drain region in the second direction;
a first contact between the first gate structure and the dummy gate structure, the first contact being in contact with the third source/drain region; and
a second contact between the second gate structure and the dummy gate structure, the second contact being in contact with the fourth source/drain region,
top surfaces of the first and second contacts being at a substantially same level as a top surface of the connection contact.

8. The semiconductor device of claim 7 , wherein the first contact, the second contact, and the connection contact include the same materials each other.

9. The semiconductor device of claim 7 , wherein
the first and second contacts have bar shapes extending in the second direction, and
the first and second contacts are spaced apart from the connection contact in the second direction.

10. The semiconductor device of claim 7 , wherein
each of the first contact, the second contact, and the connection contact has a width in the first direction when viewed in a plane view, and
the width of the connection contact is greater than the widths of the first and second contacts.

11. The semiconductor device of claim 7 , further comprising:
a plurality of logic cells on the substrate, the plurality of logic cells including,
a first logic cell, and
a second logic cell spaced apart from the first logic cell in the second direction,

each of the first gate structure, the second gate structure, and the dummy gate structure intersecting the first logic cell and the second logic cell,
the first logic cell including the first and second source/drain regions on the first active pattern, and
the second logic cell including the third and fourth source/drain regions on the second active pattern.

12. The semiconductor device of claim 11 , further comprising:
a via-contact in contact with the top surface of the connection contact,
wherein the common conductive line is in contact with a top surface of the via-contact, and
the common conductive line is configured to apply a drain voltage or a source voltage to the first and second source/drain regions through the via-contact and the connection contact.

13. The semiconductor device of claim 7 , further comprising:
a plurality of logic cells on the substrate, the plurality of logic cells including,
a first logic cell,
a second logic cell spaced apart from a first logic cell in the first direction,
a third logic cell spaced apart from the first logic cell in the second direction, and
a fourth logic cell spaced apart from the second logic cell in the second direction,

the first gate structure intersecting the first logic cell and the third logic cell,
the second gate structure intersecting the second logic cell and the fourth logic cell
the dummy gate structure being between the first logic cell and the second logic cell and between the third logic cell and the fourth logic cell,
the first logic cell including the first source/drain region on the first active pattern,
the second logic cell including the second source/drain region on the first active pattern,
the third logic cell including the third source/drain region on the second active pattern, and
the fourth logic cell including the fourth source/drain region on the second active pattern.

14. The semiconductor device of claim 13 , further comprising:
a via-contact in contact with the top surface of the connection contact,
wherein the common conductive line is in contact with a top surface of the via-contact, and
the common conductive line being shared by the first logic cell and the second logic cell.

15. The semiconductor device of claim 14 , wherein the common conductive line applies the same voltage to the first and second source/drain regions through the via-contact and the connection contact.

16. The semiconductor device of claim 1 , wherein the device isolation layer is a first device isolation layer,
The device further comprising:
a second device isolation layer extending in the second direction and dividing the active pattern into a pair of active patterns spaced apart from each other in the first direction,
wherein the first gate structure and the second gate structure

Assignees

• Samsung Electronics Co Ltd

Inventors

• Azmat Raheel
• Deepak Sharma
• Park Chulhong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L2027/11875

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L2027/11829

  Electricity · mapped topic