Split and duplicate ripple circuits
US-2021397413-A1 · Dec 23, 2021 · US
using selection between two conditionally calculated carry or sum values
using selection between two conditionally calculated carry or sum values · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/507 |
| Official title | using selection between two conditionally calculated carry or sum values |
| Display label | using selection between two conditionally calculated carry or sum values |
| Total patents | 95 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 3 |
| 2016 | 14 |
| 2017 | 10 |
| 2018 | 4 |
| 2019 | 20 |
| 2020 | 7 |
| 2021 | 8 |
| 2022 | 6 |
| 2023 | 12 |
| 2024 | 6 |
| 2025 | 5 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Domino full adder based on delayed gating positive feedback
US-11093214-B2 · Aug 17, 2021 · US
Concurrent multi-bit adder
US-10824394-B2 · Nov 3, 2020 · US
Memristor-based dividers using memristors-as-drivers (MAD) gates
US-10608639-B2 · Mar 31, 2020 · US
Apparatus and methods for vector operations
US-10599745-B2 · Mar 24, 2020 · US
Apparatus and methods for vector operations
US-10592582-B2 · Mar 17, 2020 · US
Apparatus and methods for vector operations
US-10585973-B2 · Mar 10, 2020 · US
Memristor-based multipliers using memristors-as-drivers (MAD) gates
US-10558431-B2 · Feb 11, 2020 · US
Memristor-based dividers using memristors-as-drivers (mad) gates
US-2020014388-A1 · Jan 9, 2020 · US
Concurrent multi-bit adder
US-2019384573-A1 · Dec 19, 2019 · US
Operation processing device, information processing device, and information processing method
US-2019339939-A1 · Nov 7, 2019 · US
Memristor-based dividers using memristors-as-drivers (MAD) gates
US-10447271-B2 · Oct 15, 2019 · US
Concurrent multi-bit adder
US-10402165-B2 · Sep 3, 2019 · US
Memristor-based multipliers using memristors-as-drivers (mad) gates
US-2019250885-A1 · Aug 15, 2019 · US
Memristor-based dividers using memristors-as-drivers (mad) gates
US-2019245542-A1 · Aug 8, 2019 · US
Memristor-based multipliers using memristors-as-drivers (MAD) gates
US-10318242-B2 · Jun 11, 2019 · US
Memristor-based dividers using memristors-as-drivers (MAD) gates
US-10305484-B2 · May 28, 2019 · US
Apparatus and methods for vector operations
US-2019095207-A1 · Mar 28, 2019 · US
Apparatus and methods for vector operations
US-2019095206-A1 · Mar 28, 2019 · US
Apparatus and methods for vector operations
US-2019095401-A1 · Mar 28, 2019 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/507?
- CPC G06F7/507 is the Cooperative Patent Classification code for “using selection between two conditionally calculated carry or sum values.”
- How many patents are filed under CPC G06F7/507 (using selection between two conditionally calculated carry or sum values)?
- Our database includes 95 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/507 growing?
- Publication counts under this code: 6 in 2024 vs 5 in 2025 (latest complete years).