Split and duplicate ripple circuits

Patent metadata

Field	Value
Publication number	US-2021397413-A1
Application number	US-202016908423-A
Country	US
Kind code	A1
Filing date	Jun 22, 2020
Priority date	Jun 22, 2020
Publication date	Dec 23, 2021
Grant date	—

Abstract

Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

First claim

What is claimed is:

1 . An apparatus, comprising:
a circuit that comprises:
a first portion configured to generate an intermediate signal based at least in part on a set of first operations associated with one or more input signals for the circuit, wherein the intermediate signal is one of a plurality of potential intermediate signals for the set of the first operations;
a second portion configured to generate a first potential set of one or more output signals for the circuit based at least in part on a first potential intermediate signal of the plurality and a first set of second operations;
a third portion configured to generate a second potential set of one or more output signals for the circuit based at least in part on a second potential intermediate signal of the plurality and a second set of the second operations; and
a selection component configured to select, based at least in part on the intermediate signal generated by the first portion of the circuit, between at least the first potential set of one or more output signals generated by the second portion and the second potential set of one or more output signals generated by the third portion, wherein the circuit is configured to output a set of one or more output signals based at least in part on the selection.

2 . The apparatus of claim 1 , wherein the second portion of the circuit is configured to perform at least one of the first set of the second operations concurrent with the third portion of the circuit performing at least one of the second set of the second operations.

3 . The apparatus of claim 2 , wherein the first portion of the circuit is configured to perform at least one of the set of the first operations concurrent with the second portion of the circuit performing at least one of the first set of the second operations and with the third portion of the circuit performing at least one of the second set of the second operations.

4 . The apparatus of claim 1 , wherein:
the second portion of the circuit comprises a set of one or more components; and the third portion of the circuit comprises a duplicate set of the one or more components.

5 . The apparatus of claim 1 , wherein:
the second portion of the circuit is further configured to perform the first set of the second operations based at least in part on one or more additional input signals for the circuit; and the third portion of the circuit is further configured to perform the second set of the second operations based at least in part on the one or more additional input signals for the circuit.

6 . The apparatus of claim 1 , wherein the first portion of the circuit comprises:
a first sub-portion configured to generate an initial signal based at least in part on a first subset of the first operations, wherein the first subset of the first operations is based at least in part on the one or more input signals for the circuit, and wherein the initial signal is one of a plurality of potential initial signals for the first subset of the first operations; a second sub-portion configured to generate a first potential intermediate signal of the plurality based at least in part on a first potential initial signal of the plurality and a second subset of the first operations; a third sub-portion configured to generate a second potential intermediate signal of the plurality based at least in part on a second potential initial signal of the plurality and the second subset of the first operations; and a second selection component configured to select the intermediate signal for the first portion of the circuit based at least in part on the initial signal generated by the first sub-portion, the selecting between at least the first potential intermediate signal generated by the second sub-portion and the second potential intermediate signal generated by the third sub-portion.

7 . The apparatus of claim 1 , wherein:
the first portion of the circuit comprises a first set of adders configured to add a first subset of a first set of bits and a first subset of a second set of bits; a second subset of the first set of bits is more significant than the first subset of the first set of bits; a second subset of the second set of bits is more significant than the first subset of the second set of bits; the intermediate signal generated by the first portion of the circuit comprises a carry signal generated by an adder included in the first set of adders and configured to add a most significant bit (MSB) of the first subset of the first set of bits and an MSB of the first subset of the second set of bits; the second portion of the circuit comprises a second set of adders configured to add the second subset of the first set of bits and the second subset of the second set of bits based at least in part on a first potential state of the carry signal; the third portion of the circuit comprises a third set of adders configured to add the second subset of the first set of bits and the second subset of the second set of bits based at least in part on a second potential state of the carry signal; and the selection component comprises a set of one or more multiplexers configured to select between output signals generated by the second set of adders and output signals generated by the third set of adders.

8 . The apparatus of claim 1 , wherein:
the first portion of the circuit comprises a first set of comparators configured to compare a first subset of a first set of bits with a first subset of a second set of bits; a second subset of the first set of bits is more significant than the first subset of the first set of bits; a second subset of the second set of bits is more significant than the first subset of the second set of bits; the intermediate signal generated by the first portion of the circuit comprises a carry signal generated by a comparator included in the first set of comparators and configured to compare a most significant bit (MSB) of the first subset of the first set of bits with an MSB of the first subset of the second set of bits; the second portion of the circuit comprises a second set of comparators configured to compare the second subset of the first set of bits with the second subset of the second set of bits based at least in part on a first potential state of the carry signal; the third portion of the circuit comprises a third set of comparators configured to compare the second subset of the first set of bits with the second subset of the second set of bits based at least in part on a second potential state of the carry signal; and the selection component comprises a multiplexer configured to select between an output signal generated by the second set of comparators and an output signal generated by the third set of comparators.

9 . The apparatus of claim 1 , wherein the selection component comprises one or more multiplexers.

10 . The apparatus of claim 1 , wherein:
the first potential intermediate signal comprises a first voltage; and the second potential intermediate signal comprises a second voltage.

11 . The apparatus of claim 1 , wherein:
the first potential intermediate signal indicates a first logic value; and the second potential intermediate signal indicates a second logic value.

12 . A method, comprising:
performing, using a first portion of a circuit, a set of first operations to generate an intermediate signal based at least in part on one or more input signals for the circuit, wherein the intermediate signal is one of a plurality of potential intermediate signals for the set of the first operations; performing, using a second portion of the circuit, a first set of second operations to genera

Assignees

• Micron Technology Inc

Inventors

• Morgan Donald Martin

Classifications

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title

• G06F7/02

  Comparing digital values (G06F7/06, {G06F7/22,} G06F7/38 take precedence) · CPC title