Memristor-based dividers using memristors-as-drivers (MAD) gates

Patent metadata

Field	Value
Publication number	US-10305484-B2
Application number	US-201816114956-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	Sep 8, 2017
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

First claim

The invention claimed is:

1. An SRT divider, comprising:
a memristor connected to ground via a resistor;
a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch connected to said memristor, wherein said first and second switches are connected in series, wherein said third and fourth switches are connected in series, wherein said fifth and sixth switches are connected in series, wherein a combination of said first and second switches are connected in parallel to a combination of said third and fourth switches, wherein said combination of said third and fourth switches is connected in parallel to a combination of said fifth and sixth switches; and
a first power source connected to said first switch.

2. The SRT divider as recited in claim 1 further comprising:
a second power source connected to said third switch.

3. The SRT divider as recited in claim 2 further comprising:
a third power source connected to said fifth switch via a seventh switch.

Assignees

• Univ Texas

Inventors

• Swartzlander Earl
• Guckert Lauren

Classifications

• G06F7/535

  Dividing only · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F2207/4802

  Special implementations · CPC title

• H03K19/177 Primary

  arranged in matrix form · CPC title

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title