Apparatus and methods for vector operations

Patent metadata

Field	Value
Publication number	US-10599745-B2
Application number	US-201816172533-A
Country	US
Kind code	B2
Filing date	Oct 26, 2018
Priority date	Apr 26, 2016
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.

First claim

We claim:

1. An apparatus for vector operations in a neural network, comprising:
a controller unit configured to receive a vector subtraction instruction that includes a first address of a first vector, a second address of a second vector, and an operation code that indicates an operation to subtract the first vector from the second vector, wherein the controller unit further includes an instruction register configured to store information corresponding to operation fields in the vector subtraction instruction received from the instruction queue module;
a computation module configured to receive the first vector and the second vector from a memory external to the computation module and the controller unit in response to the vector subtraction instruction based on the first address and the second address,
wherein the first vector includes one or more first elements and the second vector includes one or more second elements, and
wherein the computation module includes:
multiple subtractors configured to parallelly respectively subtract each of the first elements from a corresponding one of the second elements to generate one or more subtraction results, and
a combiner configured to combine the one or more subtraction results into an output vector.

2. The apparatus of claim 1 ,
wherein the vector subtraction instruction further indicates a first length of the first vector, and
wherein the computation module is configured to retrieve the first vector based on the first address and the first length.

3. The apparatus of claim 1 ,
wherein the vector subtraction instruction further indicates a second length of the second vector, and
wherein the computation module is configured to retrieve the second vector based on the second address and the second length.

4. The apparatus of claim 1 , wherein the vector subtraction instruction further includes one or more register IDs that identify one or more registers configured to store the first address of the first vector, a first length of the first vector, the second address of the second vector, and a second length of the second vector.

5. The apparatus of claim 1 , wherein the controller unit comprises an instruction obtaining module configured to obtain the vector subtraction instruction from an instruction storage device external to the controller unit.

6. The apparatus of claim 5 , wherein the controller unit further comprises a decoding module configured to decode the vector subtraction instruction received from the instruction obtaining module into one or more micro-instructions.

7. The apparatus of claim 6 , wherein the controller unit further comprises an instruction queue module configured to temporarily store the vector subtraction instruction received from the decoding module and one or more previously received instructions, and retrieve the information corresponding to the operation fields in the vector subtraction instruction.

8. The apparatus of claim 7 , wherein the controller unit further comprises a dependency processing unit configured to determine whether the vector subtraction instruction has a dependency relationship with the one or more previously received instructions.

9. The apparatus of claim 8 , wherein the controller unit further comprises a storage queue module configured to store the vector subtraction instruction while the dependency processing unit is determining whether the vector subtraction instruction has the dependency relationship with the one or more previously received instructions.

10. A method for vector operations in a neural network, comprising:
receiving, by a controller unit, a vector subtraction instruction that includes a first address of a first vector, a second address of a second vector, and an operation code that indicates an operation to subtract the first vector from the second vector;
storing, by an instruction register of the controller unit, information corresponding to operation fields in the vector subtraction instruction received from the instruction queue module;
receiving, by a computation module, the first vector and the second vector from a memory external to the computation module and the controller unit in response to the vector subtraction instruction based on the first address and the second address, wherein the first vector includes one or more first elements and the second vector includes one or more second elements;
parallelly respectively subtracting, by multiple subtractors of the computation module, each of the first elements from a corresponding one of the second elements to generate one or more subtraction results; and
combining, by a combiner, the one or more subtraction results into an output vector.

11. The method of claim 10 , further comprising obtaining, by an instruction obtaining module of the controller unit, the vector subtraction instruction from an instruction storage device external to the controller unit.

12. The method of claim 11 , further comprising decoding, by a decoding module of the controller unit, the vector subtraction instruction received from the instruction obtaining module into one or more micro-instructions.

13. The method of claim 12 , further comprising temporarily storing, by an instruction queue module of the controller unit, the vector subtraction instruction received from the decoding module and one or more previously received instructions, and retrieve the information corresponding to the operation fields in the vector subtraction instruction.

14. The method of claim 13 , further comprising determining, by a dependency processing unit of the controller unit, whether the vector subtraction instruction has a dependency relationship with the one or more previously received instructions.

15. The method of claim 14 , further comprising storing, by a storage queue module of the controller unit, the vector subtraction instruction while the dependency processing unit is determining whether the vector subtraction instruction has the dependency relationship with the one or more previously received instructions.

Assignees

• Cambricon Tech Corp Ltd

Inventors

• Tao Jinhua
• Zhi Tian
• Liu Shaoli
• Chen Tianshi
• Chen Yunji

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30149

  of variable length instructions · CPC title

• G06F9/30105

  Register structure · CPC title