Memristor-based dividers using memristors-as-drivers (MAD) gates

Patent metadata

Field	Value
Publication number	US-10608639-B2
Application number	US-201916560101-A
Country	US
Kind code	B2
Filing date	Sep 4, 2019
Priority date	Sep 8, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

First claim

The invention claimed is:

1. A binary non-restoring divider, comprising:
a first memristor, wherein said first memristor is connected to a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a seventh switch, wherein an eighth switch is connected to said first and second memristors;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a ninth switch, a tenth switch and an eleventh switch; and
a fourth memristor connected in parallel to said third memristor, wherein said fourth memristor is connected to a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch and a seventeenth switch.

2. The binary non-restoring divider as recited in claim 1 , wherein said second switch is connected to ground via a resistor.

3. The binary non-restoring divider as recited in claim 1 , wherein said first memristor is connected to a first power source via a resistor.

4. The binary non-restoring divider as recited in claim 1 , wherein said first, second and seventh switches are connected to a second power source.

5. The binary non-restoring divider as recited in claim 1 , wherein said third and fourth switches are connected in series, wherein said fifth and sixth switches are connected in series, wherein a combination of said third and fourth switches is connected in parallel to a combination of said fifth and sixth switches, wherein said tenth and eleventh switches are connected in series, wherein a combination of said tenth and eleventh switches is connected in parallel to said ninth switch.

6. The binary non-restoring divider as recited in claim 5 , wherein said twelfth, thirteenth and fourteenth switches are connected in series, wherein said fifteenth and sixteenth switches are connected in parallel, wherein a combination of said fifteenth and sixteenth switches is connected in series with said seventeenth switch, wherein a combination of said twelfth, thirteenth and fourteenth switches is connected in parallel to a combination of said fifteenth, sixteenth and seventeenth switches.

7. The binary non-restoring divider as recited in claim 6 , wherein said third, fifth, ninth, tenth, twelfth, fifteenth and sixteenth switches are connected to a third power source.

8. The binary non-restoring divider as recited in claim 7 , wherein said third memristor is connected to a fourth power source.

9. The binary non-restoring divider as recited in claim 1 further comprising:
a plurality of memristors, wherein each of said plurality of memristors is connected to ground via a resistor, wherein each of said plurality of memristors is connected to a switch which is connected to a power source.

Assignees

• Univ Texas

Inventors

• Swartzlander Earl
• Guckert Lauren

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F7/535

  Dividing only · CPC title

• H03K19/177 Primary

  arranged in matrix form · CPC title

• G06F2207/4802

  Special implementations · CPC title

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title