Memristor-based dividers using memristors-as-drivers (MAD) gates

Patent metadata

Field	Value
Publication number	US-10447271-B2
Application number	US-201916384735-A
Country	US
Kind code	B2
Filing date	Apr 15, 2019
Priority date	Sep 8, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Memristor-based dividers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based dividers, such as binary non-restoring dividers and SRT dividers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of dividers. Furthermore, by using MAD gates, memristor-based dividers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based dividers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

First claim

The invention claimed is:

1. An SRT divider, comprising:
a first memristor, wherein said first memristor is connected to a first switch and a second switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a third switch, wherein a fourth switch is connected to said first and second memristors;
a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch and a tenth switch connected to said second memristor;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to an eleventh switch, a twelfth switch and a thirteenth switch; and
a fourth memristor connected in parallel to said third memristor, wherein said fourth memristor is connected to a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventeenth switch, an eighteenth switch and a nineteenth switch.

2. The SRT divider as recited in claim 1 , wherein said second switch is connected to ground via a resistor.

3. The SRT divider as recited in claim 1 , wherein said first memristor is connected to a first power source via a resistor.

4. The SRT divider as recited in claim 1 , wherein said first, second and third switches are connected to a second power source.

5. The SRT divider as recited in claim 1 , wherein said fifth, sixth and seventh switches are connected in series, wherein said eighth, ninth and tenth switches are connected in series, wherein a combination of said fifth, sixth and seventh switches is connected in parallel to a combination of said eighth, ninth and tenth switches.

6. The SRT divider as recited in claim 5 , wherein said twelfth and thirteen switches are connected in series, wherein a combination of said twelfth and thirteen switches is connected in parallel to said eleventh switch.

7. The SRT divider as recited in claim 6 , wherein said fourteenth, fifteenth and sixteenth switches are connected in series, wherein said seventeenth and eighteenth switches are connected in parallel, wherein a combination of said seventeenth and eighteenth switches is connected in series with said nineteenth switch, wherein a combination of said fourteenth, fifteenth and sixteenth switches is connected in parallel to a combination of said seventeenth, eighteenth and nineteenth switches.

8. The SRT divider as recited in claim 7 , wherein said fifth, eighth, eleventh, twelfth, fourteenth, seventeenth and eighteenth are connected to a third power source.

9. The SRT divider as recited in claim 8 , wherein said third memristor is connected to a fourth power source.

Assignees

• Univ Texas

Inventors

• Swartzlander Earl
• Guckert Lauren

Classifications

• G06F2207/4802

  Special implementations · CPC title

• G06F7/535

  Dividing only · CPC title

• H03K19/177 Primary

  arranged in matrix form · CPC title

• G06F7/501

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title