Memristor-based multipliers using memristors-as-drivers (MAD) gates

Patent metadata

Field	Value
Publication number	US-10318242-B2
Application number	US-201816115123-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	Sep 8, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

First claim

The invention claimed is:

1. An array multiplier, comprising:
a first memristor connected to a first power source, a first switch and a second switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a third switch, wherein a fourth switch is connected to said first and second memristors;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a fifth switch; and
a fourth memristor connected in parallel to said third memristor, wherein said fourth memristor is connected to a sixth switch and a seventh switch.

2. The array multiplier as recited in claim 1 , wherein said first memristor is connected to said first power source via a resistor.

3. The array multiplier as recited in claim 2 , wherein said second and third switches are connected to a second power source.

4. The array multiplier as recited in claim 1 , wherein said fifth switch is connected to a third power source, wherein said third memristor is connected to a fourth power source.

5. The array multiplier as recited in claim 4 , wherein said sixth and seventh switches are connected in series, wherein said fourth memristor is connected to said fourth power source.

6. The array multiplier as recited in claim 5 , wherein said second, third and fourth memristors are connected to ground via a resistor.

7. An array multiplier, comprising:
a first memristor connected to a first power source, a first switch and a second switch;
a second memristor connected in parallel to said first memristor, wherein said second memristor is connected to a third switch, wherein a fourth switch is connected to said first and second memristors;
a third memristor connected in parallel to said second memristor, wherein said third memristor is connected to a fifth switch, a sixth switch and a seventh switch; and
a fourth memristor connected in parallel to said third memristor, wherein said fourth memristor is connected to an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch.

8. The array multiplier as recited in claim 7 , wherein said first memristor is connected to said first power source via a resistor.

9. The array multiplier as recited in claim 8 , wherein said first, second and third switches are connected to a second power source.

10. The array multiplier as recited in claim 7 , wherein said sixth and seventh switches are connected in series, wherein a combination of said sixth and seventh switches is connected in parallel to said fifth switch.

11. The array multiplier as recited in claim 10 , wherein said eighth, ninth and tenth switches are connected in series, wherein said eleventh and twelfth switches are connected in parallel, wherein a combination of said eleventh and twelfth switches is connected in series with said thirteenth switch, wherein a combination of said eleventh, twelfth and thirteenth switches is connected in parallel to a combination of said eighth, ninth and tenth switches.

12. The array multiplier as recited in claim 11 , wherein said fifth, sixth, eighth, eleventh and twelfth switches are connected to a third power source.

13. The array multiplier as recited in claim 12 , wherein said third memristor is connected to a fourth power source.

14. The array multiplier as recited in claim 7 , wherein said second, third and fourth memristors are connected to ground via a resistor.

Assignees

• Univ Texas

Inventors

• Swartzlander Earl
• Guckert Lauren

Classifications

• G06F7/507 Primary

  using selection between two conditionally calculated carry or sum values · CPC title

• G11C13/003

  Cell access · CPC title

• G06F2207/4802

  Special implementations · CPC title

• G11C13/0021

  Auxiliary circuits · CPC title

• G06F7/501

  Half or full adders, i.e. basic adder cells for one denomination · CPC title